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    Searched refs:UVD_MPC_SET_MUXB0__VARB_1__SHIFT (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c 833 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1016 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
amdgpu_vcn_v2_0.c 805 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
929 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
amdgpu_vcn_v2_5.c 813 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
956 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h 517 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x00000006
uvd_4_2_sh_mask.h 502 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
uvd_5_0_sh_mask.h 534 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
uvd_6_0_sh_mask.h 536 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
uvd_7_0_sh_mask.h 619 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h 1126 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
vcn_2_0_0_sh_mask.h 2632 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
vcn_2_5_sh_mask.h 2867 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6

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