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Searched refs:UVD_MPC_SET_MUXB0__VARB_3__SHIFT (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`835 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) \| 1018 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) \|`
amdgpu_vcn_v2_0.c	`807 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) \| 931 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) \|`
amdgpu_vcn_v2_5.c	`815 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) \| 958 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) \|`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h	`521 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x00000012`
uvd_4_2_sh_mask.h	`506 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12`
uvd_5_0_sh_mask.h	`538 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12`
uvd_6_0_sh_mask.h	`540 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12`
uvd_7_0_sh_mask.h	`621 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`1128 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12`
vcn_2_0_0_sh_mask.h	`2634 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12`
vcn_2_5_sh_mask.h	`2869 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12`

Completed in 59 milliseconds