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Searched refs:UVD_MPC_SET_MUX__SET_0__SHIFT (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`839 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) \| 1022 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) \|`
amdgpu_vcn_v2_0.c	`812 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) \| 936 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) \|`
amdgpu_vcn_v2_5.c	`820 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) \| 963 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) \|`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h	`531 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x00000000`
uvd_4_2_sh_mask.h	`516 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0`
uvd_5_0_sh_mask.h	`548 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0`
uvd_6_0_sh_mask.h	`550 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0`
uvd_7_0_sh_mask.h	`636 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`1143 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0`
vcn_2_0_0_sh_mask.h	`2649 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0`
vcn_2_5_sh_mask.h	`2884 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0`

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