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Searched refs:UVD_MPC_SET_MUX__SET_1__SHIFT (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`840 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) \| 1023 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) \|`
amdgpu_vcn_v2_0.c	`813 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) \| 937 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) \|`
amdgpu_vcn_v2_5.c	`821 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) \| 964 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) \|`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h	`533 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x00000003`
uvd_4_2_sh_mask.h	`518 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3`
uvd_5_0_sh_mask.h	`550 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3`
uvd_6_0_sh_mask.h	`552 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3`
uvd_7_0_sh_mask.h	`637 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`1144 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3`
vcn_2_0_0_sh_mask.h	`2650 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3`
vcn_2_5_sh_mask.h	`2885 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3`

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