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Searched refs:UVD_MPC_SET_MUX__SET_2__SHIFT (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`841 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1024 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);`
amdgpu_vcn_v2_0.c	`814 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 938 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));`
amdgpu_vcn_v2_5.c	`822 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 965 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h	`535 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x00000006`
uvd_4_2_sh_mask.h	`520 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6`
uvd_5_0_sh_mask.h	`552 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6`
uvd_6_0_sh_mask.h	`554 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6`
uvd_7_0_sh_mask.h	`638 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`1145 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6`
vcn_2_0_0_sh_mask.h	`2651 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6`
vcn_2_5_sh_mask.h	`2886 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6`

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