HomeSort by: relevance | last modified time | path
    Searched refs:UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h 54 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4
vcn_2_0_0_sh_mask.h 1489 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4
vcn_2_5_sh_mask.h 1492 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c 765 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
amdgpu_vcn_v2_0.c 738 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT

Completed in 115 milliseconds