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Searched refs:UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT (Results 1 - 4 of 4) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`62 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14`
vcn_2_0_0_sh_mask.h	`1497 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14`
vcn_2_5_sh_mask.h	`1500 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`773 \| 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);`

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