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Searched refs:UVD_POWER_STATUS__UVD_PG_EN_MASK (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`731 data \|= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON \| UVD_POWER_STATUS__UVD_PG_EN_MASK; 973 tmp \|= UVD_POWER_STATUS__UVD_PG_EN_MASK;`
amdgpu_vcn_v2_0.c	`705 UVD_POWER_STATUS__UVD_PG_EN_MASK; 760 tmp \|= UVD_POWER_STATUS__UVD_PG_EN_MASK;`
amdgpu_uvd_v6_0.c	`1459 WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);`
amdgpu_uvd_v7_0.c	`1741 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);`
amdgpu_vcn_v2_5.c	`768 tmp \|= UVD_POWER_STATUS__UVD_PG_EN_MASK;`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_5_0_sh_mask.h	`941 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100`
uvd_6_0_sh_mask.h	`929 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100`
uvd_7_0_sh_mask.h	`44 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`85 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L`
vcn_2_0_0_sh_mask.h	`1522 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L`
vcn_2_5_sh_mask.h	`1525 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L`

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