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Searched refs:UVD_POWER_STATUS__UVD_PG_MODE_MASK (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`972 tmp \|= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 1191 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);`
amdgpu_vcn_v2_0.c	`759 tmp \|= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 1066 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);`
amdgpu_vcn_v2_5.c	`767 tmp \|= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 1296 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);`
amdgpu_uvd_v6_0.c	`713 WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);`
amdgpu_uvd_v7_0.c	`950 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_5_0_sh_mask.h	`931 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4`
uvd_6_0_sh_mask.h	`919 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4`
uvd_7_0_sh_mask.h	`39 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`83 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L`
vcn_2_0_0_sh_mask.h	`1520 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L`
vcn_2_5_sh_mask.h	`1523 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L`

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