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Searched refs:UVD_SUVD_CGC_GATE__SRE_HEVC_MASK (Results 1 - 10 of 10) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v6_0.c	`651 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK \| 684 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK \| 1266 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK \|`
amdgpu_vcn_v1_0.c	`529 \| UVD_SUVD_CGC_GATE__SRE_HEVC_MASK`
amdgpu_vcn_v2_0.c	`522 \| UVD_SUVD_CGC_GATE__SRE_HEVC_MASK`
amdgpu_vcn_v2_5.c	`612 \| UVD_SUVD_CGC_GATE__SRE_HEVC_MASK`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_5_0_sh_mask.h	`737 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40`
uvd_6_0_sh_mask.h	`739 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40`
uvd_7_0_sh_mask.h	`234 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`462 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L`
vcn_2_0_0_sh_mask.h	`3217 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L`
vcn_2_5_sh_mask.h	`2091 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L`

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