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Searched refs:UVD_VCPU_CNTL__CLK_EN_MASK (Results 1 - 13 of 13) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v2_5.c	`779 tmp \|= UVD_VCPU_CNTL__CLK_EN_MASK; 840 tmp \|= UVD_VCPU_CNTL__CLK_EN_MASK; 926 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1350 ~(UVD_VCPU_CNTL__CLK_EN_MASK));`
amdgpu_vcn_v2_0.c	`771 tmp \|= UVD_VCPU_CNTL__CLK_EN_MASK; 900 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1109 ~(UVD_VCPU_CNTL__CLK_EN_MASK));`
amdgpu_vcn_v1_0.c	`850 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 981 tmp \|= UVD_VCPU_CNTL__CLK_EN_MASK; 1144 ~UVD_VCPU_CNTL__CLK_EN_MASK);`
amdgpu_uvd_v7_0.c	`889 UVD_VCPU_CNTL__CLK_EN_MASK); 1020 UVD_VCPU_CNTL__CLK_EN_MASK);`
amdgpu_uvd_v6_0.c	`773 WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h	`770 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L`
uvd_4_2_sh_mask.h	`549 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200`
uvd_5_0_sh_mask.h	`581 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200`
uvd_6_0_sh_mask.h	`583 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200`
uvd_7_0_sh_mask.h	`667 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`1189 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L`
vcn_2_0_0_sh_mask.h	`2761 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L`
vcn_2_5_sh_mask.h	`2761 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L`

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