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Searched refs:UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK (Results 1 - 6 of 6) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_5_0_sh_mask.h	`591 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000`
uvd_6_0_sh_mask.h	`593 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`1190 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L`
vcn_2_0_0_sh_mask.h	`2765 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`982 tmp \|= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;`
amdgpu_vcn_v2_0.c	`772 tmp \|= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;`

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