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Searched refs:VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 (Results 1 - 5 of 5) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/
amdgpu_irq_service_dce110.c	`169 .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\ 333 case VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0:`
/src/sys/external/bsd/drm2/dist/drm/amd/include/ivsrcid/
ivsrcid_vislands30.h	`68 #define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 19 // 0x13`
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/
amdgpu_irq_service_dce120.c	`164 .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\`
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce80/
amdgpu_irq_service_dce80.c	`173 .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\`
/src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm.c	`2188 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {`

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