1 /* $NetBSD: ivsrcid_vislands30.h,v 1.2 2021/12/18 23:45:24 riastradh Exp $ */ 2 3 /* 4 * Volcanic Islands IV SRC Register documentation 5 * 6 * Copyright (C) 2015 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef _IVSRCID_VISLANDS30_H_ 27 #define _IVSRCID_VISLANDS30_H_ 28 29 30 // IV Source IDs 31 32 #define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT 7 // 0x07 33 #define VISLANDS30_IV_EXTID_D1_V_UPDATE_INT 0 34 35 #define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP 8 // 0x08 36 #define VISLANDS30_IV_EXTID_D1_GRPH_PFLIP 0 37 38 #define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT 9 // 0x09 39 #define VISLANDS30_IV_EXTID_D2_V_UPDATE_INT 0 40 41 #define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP 10 // 0x0a 42 #define VISLANDS30_IV_EXTID_D2_GRPH_PFLIP 0 43 44 #define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT 11 // 0x0b 45 #define VISLANDS30_IV_EXTID_D3_V_UPDATE_INT 0 46 47 #define VISLANDS30_IV_SRCID_D3_GRPH_PFLIP 12 // 0x0c 48 #define VISLANDS30_IV_EXTID_D3_GRPH_PFLIP 0 49 50 #define VISLANDS30_IV_SRCID_D4_V_UPDATE_INT 13 // 0x0d 51 #define VISLANDS30_IV_EXTID_D4_V_UPDATE_INT 0 52 53 #define VISLANDS30_IV_SRCID_D4_GRPH_PFLIP 14 // 0x0e 54 #define VISLANDS30_IV_EXTID_D4_GRPH_PFLIP 0 55 56 #define VISLANDS30_IV_SRCID_D5_V_UPDATE_INT 15 // 0x0f 57 #define VISLANDS30_IV_EXTID_D5_V_UPDATE_INT 0 58 59 #define VISLANDS30_IV_SRCID_D5_GRPH_PFLIP 16 // 0x10 60 #define VISLANDS30_IV_EXTID_D5_GRPH_PFLIP 0 61 62 #define VISLANDS30_IV_SRCID_D6_V_UPDATE_INT 17 // 0x11 63 #define VISLANDS30_IV_EXTID_D6_V_UPDATE_INT 0 64 65 #define VISLANDS30_IV_SRCID_D6_GRPH_PFLIP 18 // 0x12 66 #define VISLANDS30_IV_EXTID_D6_GRPH_PFLIP 0 67 68 #define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 19 // 0x13 69 #define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT0 7 70 71 #define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT1 19 // 0x13 72 #define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT1 8 73 74 #define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT2 19 // 0x13 75 #define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT2 9 76 77 #define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC_LOSS 19 // 0x13 78 #define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC_LOSS 10 79 80 #define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC 19 // 0x13 81 #define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC 11 82 83 #define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SIGNAL 19 // 0x13 84 #define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SIGNAL 12 85 86 #define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0 20 // 0x14 87 #define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT0 7 88 89 #define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT1 20 // 0x14 90 #define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT1 8 91 92 #define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT2 20 // 0x14 93 #define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT2 9 94 95 #define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC_LOSS 20 // 0x14 96 #define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC_LOSS 10 97 98 #define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC 20 // 0x14 99 #define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC 11 100 101 #define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SIGNAL 20 // 0x14 102 #define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SIGNAL 12 103 104 #define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0 21 // 0x15 105 #define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT0 7 106 107 #define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT1 21 // 0x15 108 #define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT1 8 109 110 #define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT2 21 // 0x15 111 #define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT2 9 112 113 #define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC_LOSS 21 // 0x15 114 #define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC_LOSS 10 115 116 #define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC 21 // 0x15 117 #define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC 11 118 119 #define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SIGNAL 21 // 0x15 120 #define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SIGNAL 12 121 122 #define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0 22 // 0x16 123 #define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT0 7 124 125 #define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT1 22 // 0x16 126 #define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT1 8 127 128 #define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT2 22 // 0x16 129 #define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT2 9 130 131 #define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC_LOSS 22 // 0x16 132 #define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC_LOSS 10 133 134 #define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC 22 // 0x16 135 #define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC 11 136 137 #define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SIGNAL 22 // 0x16 138 #define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SIGNAL 12 139 140 #define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0 23 // 0x17 141 #define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT0 7 142 143 #define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT1 23 // 0x17 144 #define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT1 8 145 146 #define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT2 23 // 0x17 147 #define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT2 9 148 149 #define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC_LOSS 23 // 0x17 150 #define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC_LOSS 10 151 152 #define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC 23 // 0x17 153 #define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC 11 154 155 #define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SIGNAL 23 // 0x17 156 #define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SIGNAL 12 157 158 #define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0 24 // 0x18 159 #define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT0 7 160 161 #define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT1 24 // 0x18 162 #define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT1 8 163 164 #define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT2 24 // 0x18 165 #define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT2 9 166 167 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A 42 // 0x2a 168 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A 0 169 170 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_B 42 // 0x2a 171 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B 1 172 173 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_C 42 // 0x2a 174 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C 2 175 176 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_D 42 // 0x2a 177 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D 3 178 179 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_E 42 // 0x2a 180 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E 4 181 182 #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_F 42 // 0x2a 183 #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F 5 184 185 #define VISLANDS30_IV_SRCID_HPD_RX_A 42 // 0x2a 186 #define VISLANDS30_IV_EXTID_HPD_RX_A 6 187 188 #define VISLANDS30_IV_SRCID_HPD_RX_B 42 // 0x2a 189 #define VISLANDS30_IV_EXTID_HPD_RX_B 7 190 191 #define VISLANDS30_IV_SRCID_HPD_RX_C 42 // 0x2a 192 #define VISLANDS30_IV_EXTID_HPD_RX_C 8 193 194 #define VISLANDS30_IV_SRCID_HPD_RX_D 42 // 0x2a 195 #define VISLANDS30_IV_EXTID_HPD_RX_D 9 196 197 #define VISLANDS30_IV_SRCID_HPD_RX_E 42 // 0x2a 198 #define VISLANDS30_IV_EXTID_HPD_RX_E 10 199 200 #define VISLANDS30_IV_SRCID_HPD_RX_F 42 // 0x2a 201 #define VISLANDS30_IV_EXTID_HPD_RX_F 11 202 203 #define VISLANDS30_IV_SRCID_GPIO_19 0x00000053 /* 83 */ 204 205 #define VISLANDS30_IV_SRCID_SRBM_READ_TIMEOUT_ERR 0x00000060 /* 96 */ 206 #define VISLANDS30_IV_SRCID_SRBM_CTX_SWITCH 0x00000061 /* 97 */ 207 208 #define VISLANDS30_IV_SRBM_REG_ACCESS_ERROR 0x00000062 /* 98 */ 209 210 211 #define VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP 0x00000077 /* 119 */ 212 #define VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE 0x0000007c /* 124 */ 213 214 #define VISLANDS30_IV_SRCID_BIF_PF_VF_MSGBUF_VALID 0x00000087 /* 135 */ 215 216 #define VISLANDS30_IV_SRCID_BIF_VF_PF_MSGBUF_ACK 0x0000008a /* 138 */ 217 218 #define VISLANDS30_IV_SRCID_SYS_PAGE_INV_FAULT 0x0000008c /* 140 */ 219 #define VISLANDS30_IV_SRCID_SYS_MEM_PROT_FAULT 0x0000008d /* 141 */ 220 221 #define VISLANDS30_IV_SRCID_SEM_PAGE_INV_FAULT 0x00000090 /* 144 */ 222 #define VISLANDS30_IV_SRCID_SEM_MEM_PROT_FAULT 0x00000091 /* 145 */ 223 224 #define VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT 0x00000092 /* 146 */ 225 #define VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT 0x00000093 /* 147 */ 226 227 #define VISLANDS30_IV_SRCID_ACP 0x000000a2 /* 162 */ 228 229 #define VISLANDS30_IV_SRCID_VCE_TRAP 0x000000a7 /* 167 */ 230 #define VISLANDS30_IV_EXTID_VCE_TRAP_GENERAL_PURPOSE 0 231 #define VISLANDS30_IV_EXTID_VCE_TRAP_LOW_LATENCY 1 232 #define VISLANDS30_IV_EXTID_VCE_TRAP_REAL_TIME 2 233 234 #define VISLANDS30_IV_SRCID_CP_INT_RB 0x000000b0 /* 176 */ 235 #define VISLANDS30_IV_SRCID_CP_INT_IB1 0x000000b1 /* 177 */ 236 #define VISLANDS30_IV_SRCID_CP_INT_IB2 0x000000b2 /* 178 */ 237 #define VISLANDS30_IV_SRCID_CP_PM4_RES_BITS_ERR 0x000000b4 /* 180 */ 238 #define VISLANDS30_IV_SRCID_CP_END_OF_PIPE 0x000000b5 /* 181 */ 239 #define VISLANDS30_IV_SRCID_CP_BAD_OPCODE 0x000000b7 /* 183 */ 240 #define VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT 0x000000b8 /* 184 */ 241 #define VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT 0x000000b9 /* 185 */ 242 #define VISLANDS30_IV_SRCID_CP_WAIT_MEM_SEM_FAULT 0x000000ba /* 186 */ 243 #define VISLANDS30_IV_SRCID_CP_GUI_IDLE 0x000000bb /* 187 */ 244 #define VISLANDS30_IV_SRCID_CP_GUI_BUSY 0x000000bc /* 188 */ 245 246 #define VISLANDS30_IV_SRCID_CP_COMPUTE_QUERY_STATUS 0x000000bf /* 191 */ 247 #define VISLANDS30_IV_SRCID_CP_ECC_ERROR 0x000000c5 /* 197 */ 248 249 #define CARRIZO_IV_SRCID_CP_COMPUTE_QUERY_STATUS 0x000000c7 /* 199 */ 250 251 #define VISLANDS30_IV_SRCID_CP_WAIT_REG_MEM_POLL_TIMEOUT 0x000000c0 /* 192 */ 252 #define VISLANDS30_IV_SRCID_CP_SEM_SIG_INCOMPL 0x000000c1 /* 193 */ 253 #define VISLANDS30_IV_SRCID_CP_PREEMPT_ACK 0x000000c2 /* 194 */ 254 #define VISLANDS30_IV_SRCID_CP_GENERAL_PROT_FAULT 0x000000c3 /* 195 */ 255 #define VISLANDS30_IV_SRCID_CP_GDS_ALLOC_ERROR 0x000000c4 /* 196 */ 256 #define VISLANDS30_IV_SRCID_CP_ECC_ERROR 0x000000c5 /* 197 */ 257 258 #define VISLANDS30_IV_SRCID_RLC_STRM_PERF_MONITOR 0x000000ca /* 202 */ 259 260 #define VISLANDS30_IV_SDMA_ATOMIC_SRC_ID 0x000000da /* 218 */ 261 262 #define VISLANDS30_IV_SRCID_SDMA_ECC_ERROR 0x000000dc /* 220 */ 263 264 #define VISLANDS30_IV_SRCID_SDMA_TRAP 0x000000e0 /* 224 */ 265 #define VISLANDS30_IV_SRCID_SDMA_SEM_INCOMPLETE 0x000000e1 /* 225 */ 266 #define VISLANDS30_IV_SRCID_SDMA_SEM_WAIT 0x000000e2 /* 226 */ 267 268 269 #define VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER 0x000000e5 /* 229 */ 270 271 #define VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH 0x000000e6 /* 230 */ 272 #define VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW 0x000000e7 /* 231 */ 273 274 #define VISLANDS30_IV_SRCID_GRBM_READ_TIMEOUT_ERR 0x000000e8 /* 232 */ 275 #define VISLANDS30_IV_SRCID_GRBM_REG_GUI_IDLE 0x000000e9 /* 233 */ 276 277 #define VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG 0x000000ef /* 239 */ 278 279 #define VISLANDS30_IV_SRCID_SDMA_PREEMPT 0x000000f0 /* 240 */ 280 #define VISLANDS30_IV_SRCID_SDMA_VM_HOLE 0x000000f2 /* 242 */ 281 #define VISLANDS30_IV_SRCID_SDMA_CTXEMPTY 0x000000f3 /* 243 */ 282 #define VISLANDS30_IV_SRCID_SDMA_DOORBELL_INVALID 0x000000f4 /* 244 */ 283 #define VISLANDS30_IV_SRCID_SDMA_FROZEN 0x000000f5 /* 245 */ 284 #define VISLANDS30_IV_SRCID_SDMA_POLL_TIMEOUT 0x000000f6 /* 246 */ 285 #define VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE 0x000000f7 /* 247 */ 286 287 #define VISLANDS30_IV_SRCID_CG_THERMAL_TRIG 0x000000f8 /* 248 */ 288 289 #define VISLANDS30_IV_SRCID_SMU_DISP_TIMER_TRIGGER 0x000000fd /* 253 */ 290 291 /* These are not "real" source ids defined by HW */ 292 #define VISLANDS30_IV_SRCID_VM_CONTEXT_ALL 0x00000100 /* 256 */ 293 #define VISLANDS30_IV_EXTID_VM_CONTEXT0_ALL 0 294 #define VISLANDS30_IV_EXTID_VM_CONTEXT1_ALL 1 295 296 297 /* IV Extended IDs */ 298 #define VISLANDS30_IV_EXTID_NONE 0x00000000 299 #define VISLANDS30_IV_EXTID_INVALID 0xffffffff 300 301 #endif // _IVSRCID_VISLANDS30_H_ 302
Indexes created Mon Sep 22 21:09:42 GMT 2025