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    Searched refs:VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/ivsrcid/
ivsrcid_vislands30.h 269 #define VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER 0x000000e5 /* 229 */
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_virtual.c 368 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER, &adev->crtc_irq);

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