| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| dcn21_hubp.h | 93 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
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| amdgpu_dcn21_hubp.c | 708 VMID, flip_regs->vmid);
786 PLAT_54186_wa.flip.flip_params.vmid = flip_regs->vmid;
806 flip_regs.vmid = address->vmid;
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_hubp.h | 118 HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh)
185 type VMID
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| amdgpu_dcn20_hubp.c | 693 // Program VMID reg
695 VMID, address->vmid);
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_amdkfd_gfx_v7.c | 82 uint32_t vmid:4; member in struct:TCP_WATCH_CNTL_BITS::__anondd4ee9010408
123 uint32_t queue, uint32_t vmid)
126 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
156 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
164 lock_srbm(kgd, 0, 0, 0, vmid);
175 unsigned int vmid)
188 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
190 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
192 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
[all...] |
| vid.h | 76 #define VMID(x) ((x) << 4)
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| cikd.h | 63 #define VMID(x) ((x) << 4)
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| amdgpu_amdkfd_gfx_v8.c | 80 uint32_t queue, uint32_t vmid)
83 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
113 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
121 lock_srbm(kgd, 0, 0, 0, vmid);
132 unsigned int vmid)
146 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
148 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
150 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
152 /* Mapping vmid to pasid also for IH block *
[all...] |
| amdgpu_gmc_v7_0.c | 443 int vmid; local in function:gmc_v7_0_flush_gpu_tlb_pasid
449 for (vmid = 1; vmid < 16; vmid++) {
451 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
454 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
465 * VMID 0 is the physical GPU addresses as used by the kernel.
474 * @vmid: vm instance to flush
478 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
482 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
785 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); local in function:gmc_v7_0_vm_decode_fault
1291 u32 addr, status, mc_client, vmid; local in function:gmc_v7_0_process_interrupt
[all...] |
| amdgpu_gfx_v10_0.c | 290 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
291 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
293 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
316 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
347 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
1634 int vmid; local in function:gfx_v10_0_init_gds_vmid
1642 for (vmid = 1; vmid < 16; vmid++) {
1643 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0)
4413 unsigned vmid = AMDGPU_JOB_GET_VMID(job); local in function:gfx_v10_0_ring_emit_ib_gfx
4450 unsigned vmid = AMDGPU_JOB_GET_VMID(job); local in function:gfx_v10_0_ring_emit_ib_compute
[all...] |
| amdgpu_gmc_v8_0.c | 644 int vmid; local in function:gmc_v8_0_flush_gpu_tlb_pasid
650 for (vmid = 1; vmid < 16; vmid++) {
652 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
655 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
667 * VMID 0 is the physical GPU addresses as used by the kernel.
676 * @vmid: vm instance to flush
680 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
684 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
1023 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); local in function:gmc_v8_0_vm_decode_fault
1457 u32 addr, status, mc_client, vmid; local in function:gmc_v8_0_process_interrupt
[all...] |
| amdgpu_gmc_v6_0.c | 374 static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
377 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
381 unsigned vmid, uint64_t pd_addr)
386 if (vmid < 8)
387 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
389 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8);
393 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
637 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); local in function:gmc_v6_0_vm_decode_fault
646 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n"
[all...] |
| amdgpu_nv.c | 143 u32 me, u32 pipe, u32 queue, u32 vmid)
148 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
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| amdgpu_soc15.c | 292 u32 me, u32 pipe, u32 queue, u32 vmid)
297 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
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| amdgpu_vi.c | 360 * @vmid: VMID
363 * registers are instanced per VMID, others are instanced per
367 u32 me, u32 pipe, u32 queue, u32 vmid)
372 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
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| amdgpu_gfx_v9_0.c | 779 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
780 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
782 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
809 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
840 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2442 int vmid; local in function:gfx_v9_0_init_gds_vmid
2450 for (vmid = 1; vmid < 16; vmid++) {
2451 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0)
4915 unsigned vmid = AMDGPU_JOB_GET_VMID(job); local in function:gfx_v9_0_ring_emit_ib_gfx
4948 unsigned vmid = AMDGPU_JOB_GET_VMID(job); local in function:gfx_v9_0_ring_emit_ib_compute
[all...] |
| amdgpu_gfx_v8_0.c | 3678 * Initialize compute vmid sh_mem registers
3729 int vmid; local in function:gfx_v8_0_init_gds_vmid
3737 for (vmid = 1; vmid < 16; vmid++) {
3738 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
3739 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
3740 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
3741 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
4276 /* set the RB to use vmid 0 *
6092 unsigned vmid = AMDGPU_JOB_GET_VMID(job); local in function:gfx_v8_0_ring_emit_ib_gfx
6124 unsigned vmid = AMDGPU_JOB_GET_VMID(job); local in function:gfx_v8_0_ring_emit_ib_compute
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_cik_sdma.c | 969 radeon_ring_write(ring, VMID(vm_id));
989 radeon_ring_write(ring, VMID(0));
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| nid.h | 63 #define VMID(x) (((x) & 0x7) << 0)
1344 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
1345 (((vmid) & 0xF) << 20) | \
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| cikd.h | 449 #define VMID(x) ((x) << 4)
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| radeon_cik.c | 1861 * @vmid: VMID
1864 * registers are instanced per VMID, others are instanced per
1868 u32 me, u32 pipe, u32 queue, u32 vmid)
1872 VMID(vmid & 0xf) |
4088 /* set the RB to use vmid 0 */
4511 u32 vmid; member in struct:bonaire_mqd
4570 /* set the VMID assigned */
4672 /* set MQD vmid to 0 *
5681 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT; local in function:cik_vm_decode_fault
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_smu8_smumgr.c | 207 tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
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