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    Searched refs:VM_CONTEXT1_CNTL (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfxhub_v1_0.c 228 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
229 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
231 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
233 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
236 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
238 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
240 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
242 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
244 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
246 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
    [all...]
amdgpu_mmhub_v1_0.c 251 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
252 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
254 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
256 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
259 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
261 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
263 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
265 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
267 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
269 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
    [all...]
amdgpu_gmc_v8_0.c 758 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
760 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
762 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
764 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
766 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
768 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
770 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
941 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
942 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
943 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1)
    [all...]
amdgpu_gmc_v7_0.c 539 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
541 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
543 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
545 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
547 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
549 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
704 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
705 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
706 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
amdgpu_gmc_v6_0.c 418 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
420 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
422 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
424 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
426 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
428 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
sid.h 412 #define VM_CONTEXT1_CNTL 0x505
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_ni.c 1342 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
1376 WREG32(VM_CONTEXT1_CNTL, 0);
nid.h 145 #define VM_CONTEXT1_CNTL 0x1414
cikd.h 528 #define VM_CONTEXT1_CNTL 0x1414
sid.h 410 #define VM_CONTEXT1_CNTL 0x1414
radeon_evergreen.c 2450 WREG32(VM_CONTEXT1_CNTL, 0);
2466 WREG32(VM_CONTEXT1_CNTL, 0);
2516 WREG32(VM_CONTEXT1_CNTL, 0);
evergreend.h 1142 #define VM_CONTEXT1_CNTL 0x1414
radeon_si.c 4357 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
4395 WREG32(VM_CONTEXT1_CNTL, 0);
radeon_cik.c 5507 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
5578 WREG32(VM_CONTEXT1_CNTL, 0);

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