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    Searched refs:WREG32_FIELD (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v3_0.c 170 WREG32_FIELD(VCE_RB_ARB_CTRL, VCE_CGTT_OVERRIDE, override ? 1 : 0);
254 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
256 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
308 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1);
313 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1);
315 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
321 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0);
350 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 0);
353 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
577 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1)
    [all...]
amdgpu_vce_v2_0.c 206 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
262 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1);
263 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
265 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
516 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1);
amdgpu_gfx_v8_0.c 3763 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
3980 WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);
4019 WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1);
4026 WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
4034 WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
4035 WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
4042 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);
4048 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);
4053 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
4079 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0)
    [all...]
amdgpu_uvd_v6_0.c 722 WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
725 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);
741 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);
776 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);
796 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
798 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
843 WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
amdgpu_vce_v4_0.c 722 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
727 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10);
732 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
914 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i);
933 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
amdgpu_gfx_v6_0.c 2436 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2505 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2507 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2780 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2781 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2783 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2833 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
amdgpu_amdkfd_gfx_v8.c 460 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0);
amdgpu_uvd_v4_2.c 612 WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
amdgpu.h 1110 #define WREG32_FIELD(reg, field, val) \

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