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    Searched refs:WREG32_SOC15 (Results 1 - 25 of 46) sorted by relevancy

1 2

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_mmhub_v2_0.c 59 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
61 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
64 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
66 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
76 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
77 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0);
78 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF);
81 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
83 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
89 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
    [all...]
amdgpu_gfxhub_v2_0.c 74 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
76 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
79 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
81 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
90 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
91 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0);
92 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF);
95 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
97 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
103 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
    [all...]
amdgpu_vcn_v1_0.c 304 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
306 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
308 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
311 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
313 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
316 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
320 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
323 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
325 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
327 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0)
    [all...]
amdgpu_vega10_ih.c 64 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
79 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
95 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
120 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
124 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
125 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
140 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
143 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
144 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
160 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl)
    [all...]
amdgpu_psp_v12_0.c 121 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
124 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
162 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
165 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
187 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
188 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
189 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
199 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
200 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
201 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET)
    [all...]
amdgpu_df_v1_7.c 56 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
58 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
94 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
99 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
amdgpu_mes_v10_1.c 199 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);
202 WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START,
209 WREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL, data);
213 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);
221 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data);
246 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_CNTL, 0);
253 WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START,
257 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_LO,
259 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_HI,
263 WREG32_SOC15(GC, 0, mmCP_MES_MIBOUND_LO, 0x1FFFFF)
    [all...]
amdgpu_vcn_v2_0.c 316 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
318 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
320 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
323 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
325 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
328 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
332 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
335 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
337 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
339 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0)
    [all...]
amdgpu_vcn_v2_5.c 401 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
403 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
405 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
408 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
410 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
413 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
416 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
419 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
421 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
423 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, 0)
    [all...]
amdgpu_gfx_v9_4.c 700 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
701 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0);
702 WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
703 WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL, 0);
704 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
705 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0);
707 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
708 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
709 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
710 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0)
    [all...]
amdgpu_nbio_v2_3.c 44 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
46 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
63 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
67 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
148 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
150 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
154 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
176 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
184 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
198 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl)
    [all...]
amdgpu_nbio_v7_0.c 43 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
45 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
62 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
65 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
142 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
149 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
158 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
159 WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data);
242 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
250 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl)
    [all...]
amdgpu_uvd_v7_0.c 147 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
169 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR,
172 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2,
667 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
671 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
675 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
678 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
680 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
683 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
687 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size)
    [all...]
amdgpu_gfxhub_v1_0.c 63 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
65 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
68 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
70 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
108 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
110 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
114 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
116 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
193 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
198 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
    [all...]
amdgpu_navi10_ih.c 56 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
73 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
75 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
76 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
127 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8);
128 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff);
140 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
144 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
147 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
149 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI
    [all...]
amdgpu_mmhub_v1_0.c 79 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
81 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
84 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
86 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
96 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
97 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
98 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
101 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
111 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
115 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR
    [all...]
amdgpu_psp_v3_1.c 161 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
164 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
224 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
227 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
279 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
280 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
281 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
291 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
292 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
293 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET)
    [all...]
amdgpu_jpeg_v2_5.c 270 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
278 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
285 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
298 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
326 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
328 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
340 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0);
341 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
342 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
344 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH
    [all...]
amdgpu_gfx_v10_0.c 1112 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1122 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1519 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1616 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1617 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1706 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
1712 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
1753 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1759 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1785 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp)
    [all...]
amdgpu_athub_v1_0.c 50 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
67 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
amdgpu_athub_v2_0.c 53 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
71 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
amdgpu_nbio_v6_1.c 51 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
55 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
109 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
111 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
115 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
131 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
139 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
147 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
amdgpu_vcn.h 71 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
72 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
82 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \
83 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
84 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
116 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
126 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA, value); \
127 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
amdgpu_nbio_v7_4.c 65 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
67 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
84 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
87 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
177 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,
179 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,
183 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
197 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
248 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
256 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_smu9_smumgr.c 106 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_101, msg);
108 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
128 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103, 0);
130 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
161 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103, 0);
162 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102, parameter);
164 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
165 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);

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