Home | History | Annotate | Line # | Download | only in riscv
      1 /*	$NetBSD: bus_dma.c,v 1.11 2025/09/26 07:22:20 skrll Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1996, 1997, 1998, 2020 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
      9  * NASA Ames Research Center.
     10  *
     11  * Redistribution and use in source and binary forms, with or without
     12  * modification, are permitted provided that the following conditions
     13  * are met:
     14  * 1. Redistributions of source code must retain the above copyright
     15  *    notice, this list of conditions and the following disclaimer.
     16  * 2. Redistributions in binary form must reproduce the above copyright
     17  *    notice, this list of conditions and the following disclaimer in the
     18  *    documentation and/or other materials provided with the distribution.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30  * POSSIBILITY OF SUCH DAMAGE.
     31  */
     32 
     33 #define _RISCV_BUS_DMA_PRIVATE
     34 #define _RISCV_NEED_BUS_DMA_BOUNCE
     35 
     36 #include <sys/cdefs.h>
     37 __KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.11 2025/09/26 07:22:20 skrll Exp $");
     38 
     39 #include <sys/param.h>
     40 
     41 #include <sys/bus.h>
     42 #include <sys/cpu.h>
     43 #include <sys/kmem.h>
     44 #include <sys/mbuf.h>
     45 
     46 #include <uvm/uvm.h>
     47 
     48 #include <machine/cpufunc.h>
     49 
     50 #define BUSDMA_COUNTERS
     51 #ifdef BUSDMA_COUNTERS
     52 static struct evcnt bus_dma_creates =
     53 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "creates");
     54 static struct evcnt bus_dma_bounced_creates =
     55 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "bounced creates");
     56 static struct evcnt bus_dma_loads =
     57 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "loads");
     58 static struct evcnt bus_dma_bounced_loads =
     59 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "bounced loads");
     60 static struct evcnt bus_dma_coherent_loads =
     61 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "coherent loads");
     62 static struct evcnt bus_dma_read_bounces =
     63 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "read bounces");
     64 static struct evcnt bus_dma_write_bounces =
     65 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "write bounces");
     66 static struct evcnt bus_dma_bounced_unloads =
     67 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "bounced unloads");
     68 static struct evcnt bus_dma_bounced_mbuf_loads =
     69 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "bounced mbuf loads");
     70 static struct evcnt bus_dma_unloads =
     71 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "unloads");
     72 static struct evcnt bus_dma_bounced_destroys =
     73 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "bounced destroys");
     74 static struct evcnt bus_dma_destroys =
     75 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "destroys");
     76 static struct evcnt bus_dma_sync_prereadwrite =
     77 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "sync prereadwrite");
     78 static struct evcnt bus_dma_sync_preread_begin =
     79 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "sync preread begin");
     80 static struct evcnt bus_dma_sync_preread =
     81 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "sync preread");
     82 static struct evcnt bus_dma_sync_preread_tail =
     83 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "sync preread tail");
     84 static struct evcnt bus_dma_sync_prewrite =
     85 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "sync prewrite");
     86 static struct evcnt bus_dma_sync_postread =
     87 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "sync postread");
     88 static struct evcnt bus_dma_sync_postreadwrite =
     89 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "sync postreadwrite");
     90 static struct evcnt bus_dma_sync_postwrite =
     91 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "sync postwrite");
     92 static struct evcnt bus_dma_inrange_fail =
     93 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "inrange check failed");
     94 
     95 static struct evcnt bus_dma_sync_coherent_prereadwrite =
     96 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "sync coherent prereadwrite");
     97 static struct evcnt bus_dma_sync_coherent_preread =
     98 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "sync coherent preread");
     99 static struct evcnt bus_dma_sync_coherent_prewrite =
    100 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "sync coherent prewrite");
    101 static struct evcnt bus_dma_sync_coherent_postread =
    102 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "sync coherent postread");
    103 static struct evcnt bus_dma_sync_coherent_postreadwrite =
    104 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "sync coherent postreadwrite");
    105 static struct evcnt bus_dma_sync_coherent_postwrite =
    106 	EVCNT_INITIALIZER(EVCNT_TYPE_MISC, NULL, "busdma", "sync coherent postwrite");
    107 
    108 EVCNT_ATTACH_STATIC(bus_dma_creates);
    109 EVCNT_ATTACH_STATIC(bus_dma_bounced_creates);
    110 EVCNT_ATTACH_STATIC(bus_dma_loads);
    111 EVCNT_ATTACH_STATIC(bus_dma_bounced_loads);
    112 EVCNT_ATTACH_STATIC(bus_dma_coherent_loads);
    113 EVCNT_ATTACH_STATIC(bus_dma_read_bounces);
    114 EVCNT_ATTACH_STATIC(bus_dma_write_bounces);
    115 EVCNT_ATTACH_STATIC(bus_dma_unloads);
    116 EVCNT_ATTACH_STATIC(bus_dma_bounced_unloads);
    117 EVCNT_ATTACH_STATIC(bus_dma_destroys);
    118 EVCNT_ATTACH_STATIC(bus_dma_bounced_destroys);
    119 EVCNT_ATTACH_STATIC(bus_dma_bounced_mbuf_loads);
    120 EVCNT_ATTACH_STATIC(bus_dma_sync_prereadwrite);
    121 EVCNT_ATTACH_STATIC(bus_dma_sync_preread_begin);
    122 EVCNT_ATTACH_STATIC(bus_dma_sync_preread);
    123 EVCNT_ATTACH_STATIC(bus_dma_sync_preread_tail);
    124 EVCNT_ATTACH_STATIC(bus_dma_sync_prewrite);
    125 EVCNT_ATTACH_STATIC(bus_dma_sync_postread);
    126 EVCNT_ATTACH_STATIC(bus_dma_sync_postreadwrite);
    127 EVCNT_ATTACH_STATIC(bus_dma_sync_postwrite);
    128 EVCNT_ATTACH_STATIC(bus_dma_inrange_fail);
    129 
    130 EVCNT_ATTACH_STATIC(bus_dma_sync_coherent_prereadwrite);
    131 EVCNT_ATTACH_STATIC(bus_dma_sync_coherent_preread);
    132 EVCNT_ATTACH_STATIC(bus_dma_sync_coherent_prewrite);
    133 EVCNT_ATTACH_STATIC(bus_dma_sync_coherent_postread);
    134 EVCNT_ATTACH_STATIC(bus_dma_sync_coherent_postreadwrite);
    135 EVCNT_ATTACH_STATIC(bus_dma_sync_coherent_postwrite);
    136 
    137 #define	STAT_INCR(x)	(bus_dma_ ## x.ev_count++)
    138 #else
    139 #define	STAT_INCR(x)	__nothing
    140 #endif
    141 
    142 int	_bus_dmamap_load_buffer(bus_dma_tag_t, bus_dmamap_t, void *,
    143 	    bus_size_t, struct vmspace *, int);
    144 
    145 /*
    146  * Check to see if the specified page is in an allowed DMA range.
    147  */
    148 static inline struct riscv_dma_range *
    149 _bus_dma_paddr_inrange(struct riscv_dma_range *ranges, int nranges,
    150     bus_addr_t curaddr)
    151 {
    152 	struct riscv_dma_range *dr;
    153 	int i;
    154 
    155 	for (i = 0, dr = ranges; i < nranges; i++, dr++) {
    156 		if (curaddr >= dr->dr_sysbase &&
    157 		    curaddr < (dr->dr_sysbase + dr->dr_len))
    158 			return dr;
    159 	}
    160 
    161 	return NULL;
    162 }
    163 
    164 /*
    165  * Check to see if the specified busaddr is in an allowed DMA range.
    166  */
    167 static inline paddr_t
    168 _bus_dma_busaddr_to_paddr(bus_dma_tag_t t, bus_addr_t curaddr)
    169 {
    170 	struct riscv_dma_range *dr;
    171 	u_int i;
    172 
    173 	if (t->_nranges == 0)
    174 		return curaddr;
    175 
    176 	for (i = 0, dr = t->_ranges; i < t->_nranges; i++, dr++) {
    177 		if (dr->dr_busbase <= curaddr
    178 		    && curaddr < dr->dr_busbase + dr->dr_len)
    179 			return curaddr - dr->dr_busbase + dr->dr_sysbase;
    180 	}
    181 	panic("%s: curaddr %#" PRIxBUSADDR "not in range", __func__, curaddr);
    182 }
    183 
    184 /*
    185  * Common function to load the specified physical address into the
    186  * DMA map, coalescing segments and boundary checking as necessary.
    187  */
    188 static int
    189 _bus_dmamap_load_paddr(bus_dma_tag_t t, bus_dmamap_t map,
    190     bus_addr_t paddr, bus_size_t size, bool coherent)
    191 {
    192 	bus_dma_segment_t * const segs = map->dm_segs;
    193 	int nseg = map->dm_nsegs;
    194 	bus_addr_t lastaddr;
    195 	bus_addr_t bmask = ~(map->_dm_boundary - 1);
    196 	bus_addr_t curaddr;
    197 	bus_size_t sgsize;
    198 	uint32_t _ds_flags = coherent ? _BUS_DMAMAP_COHERENT : 0;
    199 
    200 	if (nseg > 0)
    201 		lastaddr = segs[nseg - 1].ds_addr + segs[nseg - 1].ds_len;
    202 	else
    203 		lastaddr = 0xdead;
    204 
    205  again:
    206 	sgsize = size;
    207 
    208 	/* Make sure we're in an allowed DMA range. */
    209 	if (t->_ranges != NULL) {
    210 		/* XXX cache last result? */
    211 		const struct riscv_dma_range * const dr =
    212 		    _bus_dma_paddr_inrange(t->_ranges, t->_nranges, paddr);
    213 		if (__predict_false(dr == NULL)) {
    214 			STAT_INCR(inrange_fail);
    215 			return EINVAL;
    216 		}
    217 
    218 		/*
    219 		 * If this region is coherent, mark the segment as coherent.
    220 		 */
    221 		_ds_flags |= dr->dr_flags & _BUS_DMAMAP_COHERENT;
    222 
    223 		/*
    224 		 * In a valid DMA range.  Translate the physical
    225 		 * memory address to an address in the DMA window.
    226 		 */
    227 		curaddr = (paddr - dr->dr_sysbase) + dr->dr_busbase;
    228 #if 0
    229 		printf("%p: %#" PRIxPADDR
    230 		    ": range %#" PRIxPADDR "/%#" PRIxBUSADDR
    231 		    "/%#" PRIxBUSSIZE "/%#" PRIx32 ": %#" PRIx32
    232 		    " <-- %#" PRIxBUSADDR "\n",
    233 		    t, paddr, dr->dr_sysbase, dr->dr_busbase,
    234 		    dr->dr_len, dr->dr_flags, _ds_flags, curaddr);
    235 #endif
    236 	} else
    237 		curaddr = paddr;
    238 
    239 	/*
    240 	 * Make sure we don't cross any boundaries.
    241 	 */
    242 	if (map->_dm_boundary > 0) {
    243 		bus_addr_t baddr;	/* next boundary address */
    244 
    245 		baddr = (curaddr + map->_dm_boundary) & bmask;
    246 		if (sgsize > (baddr - curaddr))
    247 			sgsize = (baddr - curaddr);
    248 	}
    249 
    250 	/*
    251 	 * Insert chunk into a segment, coalescing with the
    252 	 * previous segment if possible.
    253 	 */
    254 	if (nseg > 0 && curaddr == lastaddr &&
    255 	    segs[nseg - 1].ds_len + sgsize <= map->dm_maxsegsz &&
    256 	    ((segs[nseg - 1]._ds_flags ^ _ds_flags) & _BUS_DMAMAP_COHERENT) == 0 &&
    257 	    (map->_dm_boundary == 0 ||
    258 	     (segs[nseg - 1].ds_addr & bmask) == (curaddr & bmask))) {
    259 		/* coalesce */
    260 		segs[nseg - 1].ds_len += sgsize;
    261 	} else if (__predict_false(nseg >= map->_dm_segcnt)) {
    262 		return EFBIG;
    263 	} else {
    264 		/* new segment */
    265 		segs[nseg].ds_addr = curaddr;
    266 		segs[nseg].ds_len = sgsize;
    267 		segs[nseg]._ds_paddr = curaddr;
    268 		segs[nseg]._ds_flags = _ds_flags;
    269 		nseg++;
    270 	}
    271 
    272 	lastaddr = curaddr + sgsize;
    273 
    274 	paddr += sgsize;
    275 	size -= sgsize;
    276 	if (size > 0)
    277 		goto again;
    278 
    279 	map->_dm_flags &= (_ds_flags & _BUS_DMAMAP_COHERENT);
    280 	map->dm_nsegs = nseg;
    281 	return 0;
    282 }
    283 
    284 static int _bus_dma_uiomove(void *buf, struct uio *uio, size_t n,
    285 	    int direction);
    286 
    287 #ifdef _RISCV_NEED_BUS_DMA_BOUNCE
    288 static int _bus_dma_alloc_bouncebuf(bus_dma_tag_t t, bus_dmamap_t map,
    289 	    bus_size_t size, int flags);
    290 static void _bus_dma_free_bouncebuf(bus_dma_tag_t t, bus_dmamap_t map);
    291 
    292 static int
    293 _bus_dma_load_bouncebuf(bus_dma_tag_t t, bus_dmamap_t map, void *buf,
    294 	size_t buflen, int buftype, int flags)
    295 {
    296 	struct riscv_bus_dma_cookie * const cookie = map->_dm_cookie;
    297 	struct vmspace * const vm = vmspace_kernel();
    298 	int error;
    299 
    300 	KASSERT(cookie != NULL);
    301 	KASSERT(cookie->id_flags & _BUS_DMA_MIGHT_NEED_BOUNCE);
    302 
    303 	/*
    304 	 * Allocate bounce pages, if necessary.
    305 	 */
    306 	if ((cookie->id_flags & _BUS_DMA_HAS_BOUNCE) == 0) {
    307 		error = _bus_dma_alloc_bouncebuf(t, map, buflen, flags);
    308 		if (__predict_false(error))
    309 			return error;
    310 	}
    311 
    312 	/*
    313 	 * Since we're trying again, clear the previous attempt.
    314 	 */
    315 	map->dm_mapsize = 0;
    316 	map->dm_nsegs = 0;
    317 	map->_dm_buftype = _BUS_DMA_BUFTYPE_INVALID;
    318 	/* _bus_dmamap_load_buffer() clears this if we're not... */
    319 	map->_dm_flags |= _BUS_DMAMAP_COHERENT;
    320 
    321 	/*
    322 	 * Cache a pointer to the caller's buffer and load the DMA map
    323 	 * with the bounce buffer.
    324 	 */
    325 	cookie->id_origbuf = buf;
    326 	cookie->id_origbuflen = buflen;
    327 	error = _bus_dmamap_load_buffer(t, map, cookie->id_bouncebuf,
    328 	    buflen, vm, flags);
    329 	if (__predict_false(error))
    330 		return error;
    331 
    332 	STAT_INCR(bounced_loads);
    333 	map->dm_mapsize = buflen;
    334 	map->_dm_vmspace = vm;
    335 	map->_dm_buftype = buftype;
    336 
    337 	/* ...so _bus_dmamap_sync() knows we're bouncing */
    338 	map->_dm_flags |= _BUS_DMAMAP_IS_BOUNCING;
    339 	cookie->id_flags |= _BUS_DMA_IS_BOUNCING;
    340 	return 0;
    341 }
    342 #endif /* _RISCV_NEED_BUS_DMA_BOUNCE */
    343 
    344 /*
    345  * Common function for DMA map creation.  May be called by bus-specific
    346  * DMA map creation functions.
    347  */
    348 int
    349 _bus_dmamap_create(bus_dma_tag_t t, bus_size_t size, int nsegments,
    350     bus_size_t maxsegsz, bus_size_t boundary, int flags, bus_dmamap_t *dmamp)
    351 {
    352 	struct riscv_bus_dmamap *map;
    353 	void *mapstore;
    354 	int error = 0;
    355 
    356 #ifdef DEBUG_DMA
    357 	printf("dmamap_create: t=%p size=%#" PRIxBUSSIZE
    358 	    " nseg=%#x msegsz=%#" PRIxBUSSIZE
    359 	    " boundary=%#" PRIxBUSSIZE
    360 	    " flags=%#x\n", t, size, nsegments, maxsegsz, boundary, flags);
    361 #endif	/* DEBUG_DMA */
    362 
    363 	/*
    364 	 * Allocate and initialize the DMA map.  The end of the map
    365 	 * is a variable-sized array of segments, so we allocate enough
    366 	 * room for them in one shot.
    367 	 *
    368 	 * Note we don't preserve the WAITOK or NOWAIT flags.  Preservation
    369 	 * of ALLOCNOW notifies others that we've reserved these resources,
    370 	 * and they are not to be freed.
    371 	 *
    372 	 * The bus_dmamap_t includes one bus_dma_segment_t, hence
    373 	 * the (nsegments - 1).
    374 	 */
    375 	const size_t mapsize = sizeof(struct riscv_bus_dmamap) +
    376 	    (sizeof(bus_dma_segment_t) * (nsegments - 1));
    377 	const int zallocflags = (flags & BUS_DMA_NOWAIT) ? KM_NOSLEEP : KM_SLEEP;
    378 	if ((mapstore = kmem_intr_zalloc(mapsize, zallocflags)) == NULL)
    379 		return ENOMEM;
    380 
    381 	map = (struct riscv_bus_dmamap *)mapstore;
    382 	map->_dm_size = size;
    383 	map->_dm_segcnt = nsegments;
    384 	map->_dm_maxmaxsegsz = maxsegsz;
    385 	map->_dm_boundary = boundary;
    386 	map->_dm_flags = flags & ~(BUS_DMA_WAITOK | BUS_DMA_NOWAIT);
    387 	map->_dm_origbuf = NULL;
    388 	map->_dm_buftype = _BUS_DMA_BUFTYPE_INVALID;
    389 	map->_dm_vmspace = vmspace_kernel();
    390 	map->_dm_cookie = NULL;
    391 	map->dm_maxsegsz = maxsegsz;
    392 	map->dm_mapsize = 0;		/* no valid mappings */
    393 	map->dm_nsegs = 0;
    394 
    395 #ifdef _RISCV_NEED_BUS_DMA_BOUNCE
    396 	struct riscv_bus_dma_cookie *cookie;
    397 	int cookieflags;
    398 	void *cookiestore;
    399 
    400 	cookieflags = 0;
    401 
    402 	if (t->_may_bounce != NULL) {
    403 		error = (*t->_may_bounce)(t, map, flags, &cookieflags);
    404 		if (error != 0)
    405 			goto out;
    406 	}
    407 
    408 	if (t->_ranges != NULL) {
    409 		/*
    410 		 * If ranges are defined, we may have to bounce. The only
    411 		 * exception is if there is exactly one range that covers
    412 		 * all of physical memory.
    413 		 */
    414 		switch (t->_nranges) {
    415 		case 1:
    416 			if (t->_ranges[0].dr_sysbase == 0 &&
    417 			    t->_ranges[0].dr_len == UINTPTR_MAX) {
    418 				break;
    419 			}
    420 			/* FALLTHROUGH */
    421 		default:
    422 			cookieflags |= _BUS_DMA_MIGHT_NEED_BOUNCE;
    423 		}
    424 	}
    425 
    426 	if ((cookieflags & _BUS_DMA_MIGHT_NEED_BOUNCE) == 0) {
    427 		STAT_INCR(creates);
    428 		*dmamp = map;
    429 		return 0;
    430 	}
    431 
    432 	const size_t cookiesize = sizeof(struct riscv_bus_dma_cookie) +
    433 	    (sizeof(bus_dma_segment_t) * map->_dm_segcnt);
    434 
    435 	/*
    436 	 * Allocate our cookie.
    437 	 */
    438 	if ((cookiestore = kmem_intr_zalloc(cookiesize, zallocflags)) == NULL) {
    439 		error = ENOMEM;
    440 		goto out;
    441 	}
    442 	cookie = (struct riscv_bus_dma_cookie *)cookiestore;
    443 	cookie->id_flags = cookieflags;
    444 	map->_dm_cookie = cookie;
    445 	STAT_INCR(bounced_creates);
    446 
    447 	error = _bus_dma_alloc_bouncebuf(t, map, size, flags);
    448  out:
    449 	if (error)
    450 		_bus_dmamap_destroy(t, map);
    451 	else
    452 		*dmamp = map;
    453 #else
    454 	*dmamp = map;
    455 	STAT_INCR(creates);
    456 #endif /* _RISCV_NEED_BUS_DMA_BOUNCE */
    457 #ifdef DEBUG_DMA
    458 	printf("dmamap_create:map=%p\n", map);
    459 #endif	/* DEBUG_DMA */
    460 	return error;
    461 }
    462 
    463 /*
    464  * Common function for DMA map destruction.  May be called by bus-specific
    465  * DMA map destruction functions.
    466  */
    467 void
    468 _bus_dmamap_destroy(bus_dma_tag_t t, bus_dmamap_t map)
    469 {
    470 
    471 #ifdef DEBUG_DMA
    472 	printf("dmamap_destroy: t=%p map=%p\n", t, map);
    473 #endif	/* DEBUG_DMA */
    474 #ifdef _RISCV_NEED_BUS_DMA_BOUNCE
    475 	struct riscv_bus_dma_cookie *cookie = map->_dm_cookie;
    476 
    477 	/*
    478 	 * Free any bounce pages this map might hold.
    479 	 */
    480 	if (cookie != NULL) {
    481 		const size_t cookiesize = sizeof(struct riscv_bus_dma_cookie) +
    482 		    (sizeof(bus_dma_segment_t) * map->_dm_segcnt);
    483 
    484 		if (cookie->id_flags & _BUS_DMA_IS_BOUNCING)
    485 			STAT_INCR(bounced_unloads);
    486 		map->dm_nsegs = 0;
    487 		if (cookie->id_flags & _BUS_DMA_HAS_BOUNCE)
    488 			_bus_dma_free_bouncebuf(t, map);
    489 		STAT_INCR(bounced_destroys);
    490 		kmem_intr_free(cookie, cookiesize);
    491 	} else
    492 #endif
    493 	STAT_INCR(destroys);
    494 
    495 	if (map->dm_nsegs > 0)
    496 		STAT_INCR(unloads);
    497 
    498 	const size_t mapsize = sizeof(struct riscv_bus_dmamap) +
    499 	    (sizeof(bus_dma_segment_t) * (map->_dm_segcnt - 1));
    500 	kmem_intr_free(map, mapsize);
    501 }
    502 
    503 /*
    504  * Common function for loading a DMA map with a linear buffer.  May
    505  * be called by bus-specific DMA map load functions.
    506  */
    507 int
    508 _bus_dmamap_load(bus_dma_tag_t t, bus_dmamap_t map, void *buf,
    509     bus_size_t buflen, struct proc *p, int flags)
    510 {
    511 	struct vmspace *vm;
    512 	int error;
    513 
    514 #ifdef DEBUG_DMA
    515 	printf("dmamap_load: t=%p map=%p buf=%p len=%#" PRIxBUSSIZE
    516 	    " p=%p f=%#x\n", t, map, buf, buflen, p, flags);
    517 #endif	/* DEBUG_DMA */
    518 
    519 	if (map->dm_nsegs > 0) {
    520 #ifdef _RISCV_NEED_BUS_DMA_BOUNCE
    521 		struct riscv_bus_dma_cookie *cookie = map->_dm_cookie;
    522 		if (cookie != NULL) {
    523 			if (cookie->id_flags & _BUS_DMA_IS_BOUNCING) {
    524 				STAT_INCR(bounced_unloads);
    525 				cookie->id_flags &= ~_BUS_DMA_IS_BOUNCING;
    526 				map->_dm_flags &= ~_BUS_DMAMAP_IS_BOUNCING;
    527 			}
    528 		} else
    529 #endif
    530 		STAT_INCR(unloads);
    531 	}
    532 
    533 	/*
    534 	 * Make sure that on error condition we return "no valid mappings".
    535 	 */
    536 	map->dm_mapsize = 0;
    537 	map->dm_nsegs = 0;
    538 	map->_dm_buftype = _BUS_DMA_BUFTYPE_INVALID;
    539 	KASSERTMSG(map->dm_maxsegsz <= map->_dm_maxmaxsegsz,
    540 	    "dm_maxsegsz %" PRIuBUSSIZE " _dm_maxmaxsegsz %" PRIuBUSSIZE,
    541 	    map->dm_maxsegsz, map->_dm_maxmaxsegsz);
    542 
    543 	if (__predict_false(buflen > map->_dm_size))
    544 		return EINVAL;
    545 
    546 	if (p != NULL) {
    547 		vm = p->p_vmspace;
    548 	} else {
    549 		vm = vmspace_kernel();
    550 	}
    551 
    552 	/* _bus_dmamap_load_buffer() clears this if we're not... */
    553 	map->_dm_flags |= _BUS_DMAMAP_COHERENT;
    554 
    555 	error = _bus_dmamap_load_buffer(t, map, buf, buflen, vm, flags);
    556 	if (__predict_true(error == 0)) {
    557 		map->dm_mapsize = buflen;
    558 		map->_dm_vmspace = vm;
    559 		map->_dm_origbuf = buf;
    560 		map->_dm_buftype = _BUS_DMA_BUFTYPE_LINEAR;
    561 		if (map->_dm_flags & _BUS_DMAMAP_COHERENT) {
    562 			STAT_INCR(coherent_loads);
    563 		} else {
    564 			STAT_INCR(loads);
    565 		}
    566 		return 0;
    567 	}
    568 #ifdef _RISCV_NEED_BUS_DMA_BOUNCE
    569 	struct riscv_bus_dma_cookie * const cookie = map->_dm_cookie;
    570 	if (cookie != NULL && (cookie->id_flags & _BUS_DMA_MIGHT_NEED_BOUNCE)) {
    571 		error = _bus_dma_load_bouncebuf(t, map, buf, buflen,
    572 		    _BUS_DMA_BUFTYPE_LINEAR, flags);
    573 	}
    574 #endif
    575 	return error;
    576 }
    577 
    578 /*
    579  * Like _bus_dmamap_load(), but for mbufs.
    580  */
    581 int
    582 _bus_dmamap_load_mbuf(bus_dma_tag_t t, bus_dmamap_t map, struct mbuf *m0,
    583     int flags)
    584 {
    585 	struct mbuf *m;
    586 	int error;
    587 
    588 #ifdef DEBUG_DMA
    589 	printf("dmamap_load_mbuf: t=%p map=%p m0=%p f=%#x\n",
    590 	    t, map, m0, flags);
    591 #endif	/* DEBUG_DMA */
    592 
    593 	if (map->dm_nsegs > 0) {
    594 #ifdef _RISCV_NEED_BUS_DMA_BOUNCE
    595 		struct riscv_bus_dma_cookie *cookie = map->_dm_cookie;
    596 		if (cookie != NULL) {
    597 			if (cookie->id_flags & _BUS_DMA_IS_BOUNCING) {
    598 				STAT_INCR(bounced_unloads);
    599 				cookie->id_flags &= ~_BUS_DMA_IS_BOUNCING;
    600 				map->_dm_flags &= ~_BUS_DMAMAP_IS_BOUNCING;
    601 			}
    602 		} else
    603 #endif
    604 		STAT_INCR(unloads);
    605 	}
    606 
    607 	/*
    608 	 * Make sure that on error condition we return "no valid mappings."
    609 	 */
    610 	map->dm_mapsize = 0;
    611 	map->dm_nsegs = 0;
    612 	map->_dm_buftype = _BUS_DMA_BUFTYPE_INVALID;
    613 	KASSERTMSG(map->dm_maxsegsz <= map->_dm_maxmaxsegsz,
    614 	    "dm_maxsegsz %" PRIuBUSSIZE " _dm_maxmaxsegsz %" PRIuBUSSIZE,
    615 	    map->dm_maxsegsz, map->_dm_maxmaxsegsz);
    616 
    617 	KASSERT(m0->m_flags & M_PKTHDR);
    618 
    619 	if (__predict_false(m0->m_pkthdr.len > map->_dm_size))
    620 		return EINVAL;
    621 
    622 	/* _bus_dmamap_load_paddr() clears this if we're not... */
    623 	map->_dm_flags |= _BUS_DMAMAP_COHERENT;
    624 
    625 	error = 0;
    626 	for (m = m0; m != NULL && error == 0; m = m->m_next) {
    627 		int offset;
    628 		int remainbytes;
    629 		const struct vm_page * const *pgs;
    630 		paddr_t paddr;
    631 		int size;
    632 
    633 		if (m->m_len == 0)
    634 			continue;
    635 		/*
    636 		 * Don't allow reads in read-only mbufs.
    637 		 */
    638 		if (__predict_false(M_ROMAP(m) && (flags & BUS_DMA_READ))) {
    639 			error = EFAULT;
    640 			break;
    641 		}
    642 		switch (m->m_flags & (M_EXT | M_EXT_CLUSTER | M_EXT_PAGES)) {
    643 		case M_EXT | M_EXT_CLUSTER:
    644 			KASSERT(m->m_ext.ext_paddr != M_PADDR_INVALID);
    645 			paddr = m->m_ext.ext_paddr +
    646 			    (m->m_data - m->m_ext.ext_buf);
    647 			size = m->m_len;
    648 			error = _bus_dmamap_load_paddr(t, map, paddr, size,
    649 			    false);
    650 			break;
    651 
    652 		case M_EXT | M_EXT_PAGES:
    653 			KASSERT(m->m_ext.ext_buf <= m->m_data);
    654 			KASSERT(m->m_data <=
    655 			    m->m_ext.ext_buf + m->m_ext.ext_size);
    656 
    657 			offset = (vaddr_t)m->m_data -
    658 			    trunc_page((vaddr_t)m->m_ext.ext_buf);
    659 			remainbytes = m->m_len;
    660 
    661 			/* skip uninteresting pages */
    662 			pgs = (const struct vm_page * const *)
    663 			    m->m_ext.ext_pgs + (offset >> PAGE_SHIFT);
    664 
    665 			offset &= PAGE_MASK;	/* offset in the first page */
    666 
    667 			/* load each page */
    668 			while (remainbytes > 0) {
    669 				const struct vm_page *pg;
    670 
    671 				size = MIN(remainbytes, PAGE_SIZE - offset);
    672 
    673 				pg = *pgs++;
    674 				KASSERT(pg);
    675 				paddr = VM_PAGE_TO_PHYS(pg) + offset;
    676 
    677 				error = _bus_dmamap_load_paddr(t, map,
    678 				    paddr, size, false);
    679 				if (__predict_false(error))
    680 					break;
    681 				offset = 0;
    682 				remainbytes -= size;
    683 			}
    684 			break;
    685 
    686 		case 0:
    687 			paddr = m->m_paddr + M_BUFOFFSET(m) +
    688 			    (m->m_data - M_BUFADDR(m));
    689 			size = m->m_len;
    690 			error = _bus_dmamap_load_paddr(t, map, paddr, size,
    691 			    false);
    692 			break;
    693 
    694 		default:
    695 			error = _bus_dmamap_load_buffer(t, map, m->m_data,
    696 			    m->m_len, vmspace_kernel(), flags);
    697 		}
    698 	}
    699 	if (__predict_true(error == 0)) {
    700 		map->dm_mapsize = m0->m_pkthdr.len;
    701 		map->_dm_origbuf = m0;
    702 		map->_dm_buftype = _BUS_DMA_BUFTYPE_MBUF;
    703 		map->_dm_vmspace = vmspace_kernel();	/* always kernel */
    704 		if (map->_dm_flags & _BUS_DMAMAP_COHERENT) {
    705 			STAT_INCR(coherent_loads);
    706 		} else {
    707 			STAT_INCR(loads);
    708 		}
    709 		return 0;
    710 	}
    711 #ifdef _RISCV_NEED_BUS_DMA_BOUNCE
    712 	struct riscv_bus_dma_cookie * const cookie = map->_dm_cookie;
    713 	if (cookie != NULL && (cookie->id_flags & _BUS_DMA_MIGHT_NEED_BOUNCE)) {
    714 		error = _bus_dma_load_bouncebuf(t, map, m0, m0->m_pkthdr.len,
    715 		    _BUS_DMA_BUFTYPE_MBUF, flags);
    716 		STAT_INCR(bounced_mbuf_loads);
    717 	}
    718 #endif
    719 	return error;
    720 }
    721 
    722 /*
    723  * Like _bus_dmamap_load(), but for uios.
    724  */
    725 int
    726 _bus_dmamap_load_uio(bus_dma_tag_t t, bus_dmamap_t map, struct uio *uio,
    727     int flags)
    728 {
    729 	bus_size_t minlen, resid;
    730 	struct iovec *iov;
    731 	void *addr;
    732 	int i, error;
    733 
    734 	/*
    735 	 * Make sure that on error condition we return "no valid mappings."
    736 	 */
    737 	map->dm_mapsize = 0;
    738 	map->dm_nsegs = 0;
    739 	KASSERTMSG(map->dm_maxsegsz <= map->_dm_maxmaxsegsz,
    740 	    "dm_maxsegsz %" PRIuBUSSIZE " _dm_maxmaxsegsz %" PRIuBUSSIZE,
    741 	    map->dm_maxsegsz, map->_dm_maxmaxsegsz);
    742 
    743 	resid = uio->uio_resid;
    744 	iov = uio->uio_iov;
    745 
    746 	/* _bus_dmamap_load_buffer() clears this if we're not... */
    747 	map->_dm_flags |= _BUS_DMAMAP_COHERENT;
    748 
    749 	error = 0;
    750 	for (i = 0; i < uio->uio_iovcnt && resid != 0 && error == 0; i++) {
    751 		/*
    752 		 * Now at the first iovec to load.  Load each iovec
    753 		 * until we have exhausted the residual count.
    754 		 */
    755 		minlen = resid < iov[i].iov_len ? resid : iov[i].iov_len;
    756 		addr = (void *)iov[i].iov_base;
    757 
    758 		error = _bus_dmamap_load_buffer(t, map, addr, minlen,
    759 		    uio->uio_vmspace, flags);
    760 
    761 		resid -= minlen;
    762 	}
    763 	if (__predict_true(error == 0)) {
    764 		map->dm_mapsize = uio->uio_resid;
    765 		map->_dm_origbuf = uio;
    766 		map->_dm_buftype = _BUS_DMA_BUFTYPE_UIO;
    767 		map->_dm_vmspace = uio->uio_vmspace;
    768 		if (map->_dm_flags & _BUS_DMAMAP_COHERENT) {
    769 			STAT_INCR(coherent_loads);
    770 		} else {
    771 			STAT_INCR(loads);
    772 		}
    773 	}
    774 	return error;
    775 }
    776 
    777 /*
    778  * Like _bus_dmamap_load(), but for raw memory allocated with
    779  * bus_dmamem_alloc().
    780  */
    781 int
    782 _bus_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t map,
    783     bus_dma_segment_t *segs, int nsegs, bus_size_t size0, int flags)
    784 {
    785 
    786 	bus_size_t size;
    787 	int i, error = 0;
    788 
    789 	/*
    790 	 * Make sure that on error conditions we return "no valid mappings."
    791 	 */
    792 	map->dm_mapsize = 0;
    793 	map->dm_nsegs = 0;
    794 	KASSERT(map->dm_maxsegsz <= map->_dm_maxmaxsegsz);
    795 
    796 	if (__predict_false(size0 > map->_dm_size))
    797 		return EINVAL;
    798 
    799 	for (i = 0, size = size0; i < nsegs && size > 0; i++) {
    800 		bus_dma_segment_t *ds = &segs[i];
    801 		bus_size_t sgsize;
    802 
    803 		sgsize = MIN(ds->ds_len, size);
    804 		if (sgsize == 0)
    805 			continue;
    806 		const bool coherent =
    807 		    (ds->_ds_flags & _BUS_DMAMAP_COHERENT) != 0;
    808 		error = _bus_dmamap_load_paddr(t, map, ds->ds_addr,
    809 		    sgsize, coherent);
    810 		if (__predict_false(error != 0))
    811 			break;
    812 		size -= sgsize;
    813 	}
    814 
    815 	if (__predict_false(error != 0)) {
    816 		map->dm_mapsize = 0;
    817 		map->dm_nsegs = 0;
    818 		return error;
    819 	}
    820 
    821 	/* XXX TBD bounce */
    822 
    823 	map->dm_mapsize = size0;
    824 	map->_dm_origbuf = NULL;
    825 	map->_dm_buftype = _BUS_DMA_BUFTYPE_RAW;
    826 	map->_dm_vmspace = NULL;
    827 	return 0;
    828 }
    829 
    830 /*
    831  * Common function for unloading a DMA map.  May be called by
    832  * bus-specific DMA map unload functions.
    833  */
    834 void
    835 _bus_dmamap_unload(bus_dma_tag_t t, bus_dmamap_t map)
    836 {
    837 
    838 #ifdef DEBUG_DMA
    839 	printf("dmamap_unload: t=%p map=%p\n", t, map);
    840 #endif	/* DEBUG_DMA */
    841 
    842 	/*
    843 	 * No resources to free; just mark the mappings as
    844 	 * invalid.
    845 	 */
    846 	map->dm_mapsize = 0;
    847 	map->dm_nsegs = 0;
    848 	map->_dm_origbuf = NULL;
    849 	map->_dm_buftype = _BUS_DMA_BUFTYPE_INVALID;
    850 	map->_dm_vmspace = NULL;
    851 }
    852 
    853 static void
    854 _bus_dmamap_sync_segment(vaddr_t va, paddr_t pa, vsize_t len, int ops)
    855 {
    856 
    857 	KASSERTMSG((va & PAGE_MASK) == (pa & PAGE_MASK),
    858 	    "va %#" PRIxVADDR " pa %#" PRIxPADDR, va, pa);
    859 #if 0
    860 	printf("sync_segment: va=%#" PRIxVADDR
    861 	    " pa=%#" PRIxPADDR " len=%#" PRIxVSIZE " ops=%#x\n",
    862 	    va, pa, len, ops);
    863 #endif
    864 	switch (ops) {
    865 	case BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE:
    866 		STAT_INCR(sync_prereadwrite);
    867 		cpu_dcache_wbinv_range(va, len);
    868 		cpu_sdcache_wbinv_range(va, pa, len);
    869 		break;
    870 
    871 	case BUS_DMASYNC_PREREAD: {
    872 		const vsize_t line_size = riscv_dcache_align;
    873 		const vsize_t line_mask = riscv_dcache_align_mask;
    874 		vsize_t misalignment = va & line_mask;
    875 		if (misalignment) {
    876 			va -= misalignment;
    877 			pa -= misalignment;
    878 			len += misalignment;
    879 			STAT_INCR(sync_preread_begin);
    880 			cpu_dcache_wbinv_range(va, line_size);
    881 			cpu_sdcache_wbinv_range(va, pa, line_size);
    882 			if (len <= line_size)
    883 				break;
    884 			va += line_size;
    885 			pa += line_size;
    886 			len -= line_size;
    887 		}
    888 		misalignment = len & line_mask;
    889 		len -= misalignment;
    890 		if (len > 0) {
    891 			STAT_INCR(sync_preread);
    892 			cpu_dcache_inv_range(va, len);
    893 			cpu_sdcache_inv_range(va, pa, len);
    894 		}
    895 		if (misalignment) {
    896 			va += len;
    897 			pa += len;
    898 			STAT_INCR(sync_preread_tail);
    899 			cpu_dcache_wbinv_range(va, line_size);
    900 			cpu_sdcache_wbinv_range(va, pa, line_size);
    901 		}
    902 		break;
    903 	}
    904 
    905 	case BUS_DMASYNC_PREWRITE:
    906 		STAT_INCR(sync_prewrite);
    907 		cpu_dcache_wb_range(va, len);
    908 		cpu_sdcache_wb_range(va, pa, len);
    909 		break;
    910 
    911 	/*
    912 	 * CPUs can do speculative loads so we need to clean the cache after
    913 	 * a DMA read to deal with any speculatively loaded cache lines.
    914 	 * Since these can't be dirty, we can just invalidate them and don't
    915 	 * have to worry about having to write back their contents.
    916 	 */
    917 	case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE:
    918 		STAT_INCR(sync_postreadwrite);
    919 		cpu_dcache_inv_range(va, len);
    920 		cpu_sdcache_inv_range(va, pa, len);
    921 		break;
    922 	case BUS_DMASYNC_POSTREAD:
    923 		STAT_INCR(sync_postread);
    924 		cpu_dcache_inv_range(va, len);
    925 		cpu_sdcache_inv_range(va, pa, len);
    926 		break;
    927 	}
    928 }
    929 
    930 static inline void
    931 _bus_dmamap_sync_linear(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
    932     bus_size_t len, int ops)
    933 {
    934 	bus_dma_segment_t *ds = map->dm_segs;
    935 	vaddr_t va = (vaddr_t) map->_dm_origbuf;
    936 #ifdef _RISCV_NEED_BUS_DMA_BOUNCE
    937 	if (map->_dm_flags & _BUS_DMAMAP_IS_BOUNCING) {
    938 		struct riscv_bus_dma_cookie * const cookie = map->_dm_cookie;
    939 		va = (vaddr_t) cookie->id_bouncebuf;
    940 	}
    941 #endif
    942 
    943 	while (len > 0) {
    944 		while (offset >= ds->ds_len) {
    945 			offset -= ds->ds_len;
    946 			va += ds->ds_len;
    947 			ds++;
    948 		}
    949 
    950 		paddr_t pa = _bus_dma_busaddr_to_paddr(t, ds->ds_addr + offset);
    951 		size_t seglen = uimin(len, ds->ds_len - offset);
    952 
    953 		if ((ds->_ds_flags & _BUS_DMAMAP_COHERENT) == 0)
    954 			_bus_dmamap_sync_segment(va + offset, pa, seglen, ops);
    955 
    956 		offset += seglen;
    957 		len -= seglen;
    958 	}
    959 }
    960 
    961 static inline void
    962 _bus_dmamap_sync_mbuf(bus_dma_tag_t t, bus_dmamap_t map, bus_size_t offset,
    963     bus_size_t len, int ops)
    964 {
    965 	bus_dma_segment_t *ds = map->dm_segs;
    966 	struct mbuf *m = map->_dm_origbuf;
    967 	bus_size_t voff = offset;
    968 	bus_size_t ds_off = offset;
    969 
    970 	while (len > 0) {
    971 		/* Find the current dma segment */
    972 		while (ds_off >= ds->ds_len) {
    973 			ds_off -= ds->ds_len;
    974 			ds++;
    975 		}
    976 		/* Find the current mbuf. */
    977 		while (voff >= m->m_len) {
    978 			voff -= m->m_len;
    979 			m = m->m_next;
    980 		}
    981 
    982 		/*
    983 		 * Now at the first mbuf to sync; nail each one until
    984 		 * we have exhausted the length.
    985 		 */
    986 		vsize_t seglen = uimin(len, uimin(m->m_len - voff, ds->ds_len - ds_off));
    987 		vaddr_t va = mtod(m, vaddr_t) + voff;
    988 		paddr_t pa = _bus_dma_busaddr_to_paddr(t, ds->ds_addr + ds_off);
    989 
    990 		/*
    991 		 * If a mapping is read-only, no dirty cache blocks will
    992 		 * exist for it.  If a writable mapping was made read-only,
    993 		 * we know any dirty cache lines for the range will have
    994 		 * been cleaned for us already.  Therefore, if the upper
    995 		 * layer can tell us we have a read-only mapping, we can
    996 		 * skip all cache cleaning.
    997 		 *
    998 		 * NOTE: This only works if we know the pmap cleans pages
    999 		 * before making a read-write -> read-only transition.  Assume
   1000 		 * this is not true here.
   1001 		 *
   1002 		 * XXXNH this will have to be revisited.
   1003 		 */
   1004 
   1005 		if ((ds->_ds_flags & _BUS_DMAMAP_COHERENT) == 0) {
   1006 			/*
   1007 			 * If we are doing preread (DMAing into the mbuf),
   1008 			 * this mbuf better not be readonly,
   1009 			 */
   1010 			KASSERT(!(ops & BUS_DMASYNC_PREREAD) || !M_ROMAP(m));
   1011 			_bus_dmamap_sync_segment(va, pa, seglen, ops);
   1012 		}
   1013 		voff += seglen;
   1014 		ds_off += seglen;
   1015 		len -= seglen;
   1016 	}
   1017 }
   1018 
   1019 static inline void
   1020 _bus_dmamap_sync_uio(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
   1021     bus_size_t len, int ops)
   1022 {
   1023 	bus_dma_segment_t *ds = map->dm_segs;
   1024 	struct uio *uio = map->_dm_origbuf;
   1025 	struct iovec *iov = uio->uio_iov;
   1026 	bus_size_t voff = offset;
   1027 	bus_size_t ds_off = offset;
   1028 
   1029 	while (len > 0) {
   1030 		/* Find the current dma segment */
   1031 		while (ds_off >= ds->ds_len) {
   1032 			ds_off -= ds->ds_len;
   1033 			ds++;
   1034 		}
   1035 
   1036 		/* Find the current iovec. */
   1037 		while (voff >= iov->iov_len) {
   1038 			voff -= iov->iov_len;
   1039 			iov++;
   1040 		}
   1041 
   1042 		/*
   1043 		 * Now at the first iovec to sync; nail each one until
   1044 		 * we have exhausted the length.
   1045 		 */
   1046 		vsize_t seglen = uimin(len, uimin(iov->iov_len - voff, ds->ds_len - ds_off));
   1047 		vaddr_t va = (vaddr_t) iov->iov_base + voff;
   1048 		paddr_t pa = _bus_dma_busaddr_to_paddr(t, ds->ds_addr + ds_off);
   1049 
   1050 		if ((ds->_ds_flags & _BUS_DMAMAP_COHERENT) == 0)
   1051 			_bus_dmamap_sync_segment(va, pa, seglen, ops);
   1052 
   1053 		voff += seglen;
   1054 		ds_off += seglen;
   1055 		len -= seglen;
   1056 	}
   1057 }
   1058 
   1059 /*
   1060  * Common function for DMA map synchronization.  May be called
   1061  * by bus-specific DMA map synchronization functions.
   1062  *
   1063  * XXX Should have separate versions for write-through vs.
   1064  * XXX write-back caches.  We currently assume write-back
   1065  * XXX here, which is not as efficient as it could be for
   1066  * XXX the write-through case.
   1067  */
   1068 void
   1069 _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset,
   1070     bus_size_t len, int ops)
   1071 {
   1072 #ifdef DEBUG_DMA
   1073 	printf("dmamap_sync: t=%p map=%p offset=%#" PRIxBUSADDR
   1074 	    " len=%#" PRIxBUSSIZE " ops=%#x\n", t, map, offset, len, ops);
   1075 #endif	/* DEBUG_DMA */
   1076 
   1077 	/*
   1078 	 * Mixing of PRE and POST operations is not allowed.
   1079 	 */
   1080 	KASSERTMSG((((ops & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)) == 0)
   1081 	    || ((ops & (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)) == 0)),
   1082 	    "%s: mix PRE and POST", __func__);
   1083 
   1084 	KASSERTMSG(offset < map->dm_mapsize,
   1085 	    "offset %" PRIxBUSADDR " mapsize %" PRIuBUSSIZE,
   1086 	    offset, map->dm_mapsize);
   1087 	KASSERTMSG(len > 0 && offset + len <= map->dm_mapsize,
   1088 	    "len %" PRIuBUSSIZE " offset %" PRIxBUSADDR " mapsize %" PRIuBUSSIZE,
   1089 	    len, offset, map->dm_mapsize);
   1090 
   1091 	/*
   1092 	 * For a write-back cache, we need to do the following things:
   1093 	 *
   1094 	 *	PREREAD -- Invalidate the D-cache.  We do this
   1095 	 *	here in case a write-back is required by the back-end.
   1096 	 *
   1097 	 *	PREWRITE -- Write-back the D-cache.  Note that if
   1098 	 *	we are doing a PREREAD | PREWRITE, we can collapse
   1099 	 *	the whole thing into a single Wb-Inv.
   1100 	 *
   1101 	 *	POSTREAD -- Re-invalidate the D-cache in case speculative
   1102 	 *	memory accesses caused cachelines to become valid with now
   1103 	 *	invalid data.
   1104 	 *
   1105 	 *	POSTWRITE -- Nothing.
   1106 	 */
   1107 #ifdef _RISCV_NEED_BUS_DMA_BOUNCE
   1108 	const bool bouncing = (map->_dm_flags & _BUS_DMAMAP_IS_BOUNCING);
   1109 #else
   1110 	const bool bouncing = false;
   1111 #endif
   1112 
   1113 	const int pre_ops = ops & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
   1114 	const int post_ops = ops & (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
   1115 	if (pre_ops == 0 && post_ops == 0)
   1116 		return;
   1117 
   1118 	if (post_ops == BUS_DMASYNC_POSTWRITE) {
   1119 		KASSERT(pre_ops == 0);
   1120 		if ((map->_dm_flags & _BUS_DMAMAP_COHERENT)) {
   1121 			STAT_INCR(sync_coherent_postwrite);
   1122 		} else {
   1123 			STAT_INCR(sync_postwrite);
   1124 		}
   1125 		return;
   1126 	}
   1127 
   1128 	KASSERTMSG(bouncing || pre_ops != 0 || (post_ops & BUS_DMASYNC_POSTREAD),
   1129 	    "pre_ops %#x post_ops %#x", pre_ops, post_ops);
   1130 
   1131 	if (bouncing && (ops & BUS_DMASYNC_PREWRITE)) {
   1132 		struct riscv_bus_dma_cookie * const cookie = map->_dm_cookie;
   1133 		STAT_INCR(write_bounces);
   1134 		char * const dataptr = (char *)cookie->id_bouncebuf + offset;
   1135 		/*
   1136 		 * Copy the caller's buffer to the bounce buffer.
   1137 		 */
   1138 		switch (map->_dm_buftype) {
   1139 		case _BUS_DMA_BUFTYPE_LINEAR:
   1140 			memcpy(dataptr, cookie->id_origlinearbuf + offset, len);
   1141 			break;
   1142 
   1143 		case _BUS_DMA_BUFTYPE_MBUF:
   1144 			m_copydata(cookie->id_origmbuf, offset, len, dataptr);
   1145 			break;
   1146 
   1147 		case _BUS_DMA_BUFTYPE_UIO:
   1148 			_bus_dma_uiomove(dataptr, cookie->id_origuio, len,
   1149 			    UIO_WRITE);
   1150 			break;
   1151 
   1152 #ifdef DIAGNOSTIC
   1153 		case _BUS_DMA_BUFTYPE_RAW:
   1154 			panic("%s:(pre): _BUS_DMA_BUFTYPE_RAW", __func__);
   1155 			break;
   1156 
   1157 		case _BUS_DMA_BUFTYPE_INVALID:
   1158 			panic("%s(pre): _BUS_DMA_BUFTYPE_INVALID", __func__);
   1159 			break;
   1160 
   1161 		default:
   1162 			panic("%s(pre): map %p: unknown buffer type %d\n",
   1163 			    __func__, map, map->_dm_buftype);
   1164 			break;
   1165 #endif /* DIAGNOSTIC */
   1166 		}
   1167 	}
   1168 
   1169 	/*
   1170 	 * Provide appropriate memory barriers, and skip cache frobbing
   1171 	 * if mapping is COHERENT.
   1172 	 *
   1173 	 * The case of PREREAD is as follows:
   1174 	 *
   1175 	 * 1. loads and stores before DMA buffer may be allocated for the
   1176 	 *    purpose
   1177 	 * 2. bus_dmamap_sync(BUS_DMASYNC_PREREAD)
   1178 	 * 3. store to register or DMA descriptor to trigger DMA
   1179 	 *
   1180 	 * The load/store-before-store ordering is ensured by fence rw, ow.
   1181 	 *
   1182 	 * The case of PREWRITE is as follows:
   1183 	 *
   1184 	 * 1. stores to DMA buffer. loads can happen later as the buffer is
   1185 	 *    not changed by the device.
   1186 	 * 2. bus_dmamap_sync(BUS_DMASYNC_PREWRITE)
   1187 	 * 3. store to register or DMA descriptor to trigger DMA
   1188 	 *
   1189 	 * The store-before-store ordering is ensured by fence w,ow.
   1190 	 *
   1191 	 * The case of POSTREAD is as follows:
   1192 	 *
   1193 	 * 1. load from register or DMA descriptor notifying DMA completion
   1194 	 * 2. bus_dmamap_sync(BUS_DMASYNC_POSTREAD)
   1195 	 * 3. loads from DMA buffer to use data, and stores to reuse buffer
   1196 	 *
   1197 	 * The stores in (3) will not be speculated and, therefore, don't need
   1198 	 * specific handling. The load-before-load ordering is provided by
   1199 	 * fence ir,r.
   1200 	 *
   1201 	 * The case of POSTWRITE is as follows:
   1202 	 *
   1203 	 * 1. load from register or DMA descriptor notifying DMA completion
   1204 	 * 2. bus_dmamap_sync(BUS_DMASYNC_POSTWRITE)
   1205 	 * 3. loads and stores to reuse buffer
   1206 	 *
   1207 	 * The stores in (3) will not be speculated, and the load can happen
   1208 	 * at any time as the DMA buffer is not changed by the device so no
   1209 	 * barrier is required.
   1210 	 */
   1211 	if ((map->_dm_flags & _BUS_DMAMAP_COHERENT)) {
   1212 		switch (ops) {
   1213 		case BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE:
   1214 			asm volatile ("fence rw,ow" ::: "memory");
   1215 			STAT_INCR(sync_coherent_prereadwrite);
   1216 			break;
   1217 
   1218 		case BUS_DMASYNC_PREREAD:
   1219 			asm volatile ("fence rw,ow" ::: "memory");
   1220 			STAT_INCR(sync_coherent_preread);
   1221 			break;
   1222 
   1223 		case BUS_DMASYNC_PREWRITE:
   1224 			asm volatile ("fence w,ow" ::: "memory");
   1225 			STAT_INCR(sync_coherent_prewrite);
   1226 			break;
   1227 
   1228 		case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE:
   1229 			asm volatile ("fence ir,r" ::: "memory");
   1230 			STAT_INCR(sync_coherent_postreadwrite);
   1231 			break;
   1232 
   1233 		case BUS_DMASYNC_POSTREAD:
   1234 			asm volatile ("fence ir,r" ::: "memory");
   1235 			STAT_INCR(sync_coherent_postread);
   1236 			break;
   1237 
   1238 		/* BUS_DMASYNC_POSTWRITE was aleady handled as a fastpath */
   1239 		}
   1240 
   1241 		/*
   1242 		 * Only thing left to do for COHERENT mapping is copy from bounce
   1243 		 * in the POSTREAD case.
   1244 		 */
   1245 		if (bouncing && (post_ops & BUS_DMASYNC_POSTREAD))
   1246 			goto bounce_it;
   1247 
   1248 		return;
   1249 	}
   1250 
   1251 	int buftype = map->_dm_buftype;
   1252 	if (bouncing) {
   1253 		buftype = _BUS_DMA_BUFTYPE_LINEAR;
   1254 	}
   1255 
   1256 	switch (buftype) {
   1257 	case _BUS_DMA_BUFTYPE_LINEAR:
   1258 	case _BUS_DMA_BUFTYPE_RAW:
   1259 		_bus_dmamap_sync_linear(t, map, offset, len, ops);
   1260 		break;
   1261 
   1262 	case _BUS_DMA_BUFTYPE_MBUF:
   1263 		_bus_dmamap_sync_mbuf(t, map, offset, len, ops);
   1264 		break;
   1265 
   1266 	case _BUS_DMA_BUFTYPE_UIO:
   1267 		_bus_dmamap_sync_uio(t, map, offset, len, ops);
   1268 		break;
   1269 
   1270 	case _BUS_DMA_BUFTYPE_INVALID:
   1271 		panic("%s: _BUS_DMA_BUFTYPE_INVALID", __func__);
   1272 		break;
   1273 
   1274 	default:
   1275 		panic("%s: map %p: unknown buffer type %d\n", __func__, map,
   1276 		    map->_dm_buftype);
   1277 	}
   1278 
   1279 	/* Drain the write buffer. */
   1280 	asm volatile ("fence iorw,iorw" ::: "memory");
   1281 
   1282 	if (!bouncing || (ops & BUS_DMASYNC_POSTREAD) == 0)
   1283 		return;
   1284 
   1285   bounce_it:
   1286 	STAT_INCR(read_bounces);
   1287 
   1288 	struct riscv_bus_dma_cookie * const cookie = map->_dm_cookie;
   1289 	char * const dataptr = (char *)cookie->id_bouncebuf + offset;
   1290 	/*
   1291 	 * Copy the bounce buffer to the caller's buffer.
   1292 	 */
   1293 	switch (map->_dm_buftype) {
   1294 	case _BUS_DMA_BUFTYPE_LINEAR:
   1295 		memcpy(cookie->id_origlinearbuf + offset, dataptr, len);
   1296 		break;
   1297 
   1298 	case _BUS_DMA_BUFTYPE_MBUF:
   1299 		m_copyback(cookie->id_origmbuf, offset, len, dataptr);
   1300 		break;
   1301 
   1302 	case _BUS_DMA_BUFTYPE_UIO:
   1303 		_bus_dma_uiomove(dataptr, cookie->id_origuio, len, UIO_READ);
   1304 		break;
   1305 
   1306 #ifdef DIAGNOSTIC
   1307 	case _BUS_DMA_BUFTYPE_RAW:
   1308 		panic("%s(post): _BUS_DMA_BUFTYPE_RAW", __func__);
   1309 		break;
   1310 
   1311 	case _BUS_DMA_BUFTYPE_INVALID:
   1312 		panic("%s(post): _BUS_DMA_BUFTYPE_INVALID", __func__);
   1313 		break;
   1314 
   1315 	default:
   1316 		panic("%s(post): map %p: unknown buffer type %d\n", __func__,
   1317 		    map, map->_dm_buftype);
   1318 		break;
   1319 #endif
   1320 	}
   1321 }
   1322 
   1323 /*
   1324  * Common function for DMA-safe memory allocation.  May be called
   1325  * by bus-specific DMA memory allocation functions.
   1326  */
   1327 
   1328 int
   1329 _bus_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment,
   1330     bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs,
   1331     int flags)
   1332 {
   1333 	struct riscv_dma_range *dr;
   1334 	int error, i;
   1335 
   1336 #ifdef DEBUG_DMA
   1337 	printf("dmamem_alloc t=%p size=%#" PRIxBUSSIZE
   1338 	    " align=%#" PRIxBUSSIZE
   1339 	    " boundary=%#" PRIxBUSSIZE " "
   1340 	    "segs=%p nsegs=%#x rsegs=%p flags=%#x\n", t, size, alignment,
   1341 	    boundary, segs, nsegs, rsegs, flags);
   1342 #endif
   1343 
   1344 	if ((dr = t->_ranges) != NULL) {
   1345 		error = ENOMEM;
   1346 		for (i = 0; i < t->_nranges; i++, dr++) {
   1347 			if (dr->dr_len == 0
   1348 			    || (dr->dr_flags & _BUS_DMAMAP_NOALLOC))
   1349 				continue;
   1350 			error = _bus_dmamem_alloc_range(t, size, alignment,
   1351 			    boundary, segs, nsegs, rsegs, flags,
   1352 			    trunc_page(dr->dr_sysbase),
   1353 			    trunc_page(dr->dr_sysbase + dr->dr_len));
   1354 			if (error == 0)
   1355 				break;
   1356 		}
   1357 	} else {
   1358 		error = _bus_dmamem_alloc_range(t, size, alignment, boundary,
   1359 		    segs, nsegs, rsegs, flags, 0UL, ~0UL);
   1360 	}
   1361 
   1362 #ifdef DEBUG_DMA
   1363 	printf("dmamem_alloc: =%d\n", error);
   1364 #endif
   1365 
   1366 	return error;
   1367 }
   1368 
   1369 /*
   1370  * Common function for freeing DMA-safe memory.  May be called by
   1371  * bus-specific DMA memory free functions.
   1372  */
   1373 void
   1374 _bus_dmamem_free(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs)
   1375 {
   1376 	struct vm_page *m;
   1377 	bus_addr_t addr;
   1378 	struct pglist mlist;
   1379 	int curseg;
   1380 
   1381 #ifdef DEBUG_DMA
   1382 	printf("dmamem_free: t=%p segs=%p nsegs=%#x\n", t, segs, nsegs);
   1383 #endif	/* DEBUG_DMA */
   1384 
   1385 	/*
   1386 	 * Build a list of pages to free back to the VM system.
   1387 	 */
   1388 	TAILQ_INIT(&mlist);
   1389 	for (curseg = 0; curseg < nsegs; curseg++) {
   1390 		for (addr = segs[curseg].ds_addr;
   1391 		    addr < (segs[curseg].ds_addr + segs[curseg].ds_len);
   1392 		    addr += PAGE_SIZE) {
   1393 			m = PHYS_TO_VM_PAGE(addr);
   1394 			TAILQ_INSERT_TAIL(&mlist, m, pageq.queue);
   1395 		}
   1396 	}
   1397 	uvm_pglistfree(&mlist);
   1398 }
   1399 
   1400 /*
   1401  * Common function for mapping DMA-safe memory.  May be called by
   1402  * bus-specific DMA memory map functions.
   1403  */
   1404 int
   1405 _bus_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs,
   1406     size_t size, void **kvap, int flags)
   1407 {
   1408 	vaddr_t va;
   1409 	paddr_t pa;
   1410 	int curseg;
   1411 	const uvm_flag_t kmflags = UVM_KMF_VAONLY
   1412 	    | ((flags & BUS_DMA_NOWAIT) != 0 ? UVM_KMF_NOWAIT : 0);
   1413 	vsize_t align = 0;
   1414 
   1415 #ifdef DEBUG_DMA
   1416 	printf("dmamem_map: t=%p segs=%p nsegs=%#x size=%#zx flags=%#x\n", t,
   1417 	    segs, nsegs, size, flags);
   1418 #endif	/* DEBUG_DMA */
   1419 
   1420 #ifdef PMAP_MAP_POOLPAGE
   1421 	/*
   1422 	 * If all of memory is mapped, and we are mapping a single physically
   1423 	 * contiguous area then this area is already mapped.  Let's see if we
   1424 	 * avoid having a separate mapping for it.
   1425 	 */
   1426 	if (nsegs == 1 && (flags & BUS_DMA_PREFETCHABLE) == 0) {
   1427 		/*
   1428 		 * If this is a non-COHERENT mapping, then the existing kernel
   1429 		 * mapping is already compatible with it.
   1430 		 */
   1431 		bool direct_mapable = (flags & BUS_DMA_COHERENT) == 0;
   1432 		pa = segs[0].ds_addr;
   1433 
   1434 		/*
   1435 		 * This is a COHERENT mapping which, unless this address is in
   1436 		 * a COHERENT dma range, will not be compatible.
   1437 		 */
   1438 		if (t->_ranges != NULL) {
   1439 			const struct riscv_dma_range * const dr =
   1440 			    _bus_dma_paddr_inrange(t->_ranges, t->_nranges, pa);
   1441 			if (dr != NULL
   1442 			    && (dr->dr_flags & _BUS_DMAMAP_COHERENT)) {
   1443 				direct_mapable = true;
   1444 			}
   1445 		}
   1446 
   1447 		if (direct_mapable) {
   1448 			*kvap = (void *)PMAP_MAP_POOLPAGE(pa);
   1449 #ifdef DEBUG_DMA
   1450 			printf("dmamem_map: =%p\n", *kvap);
   1451 #endif	/* DEBUG_DMA */
   1452 			return 0;
   1453 		}
   1454 	}
   1455 #endif
   1456 
   1457 	size = round_page(size);
   1458 
   1459 #ifdef PMAP_MAPSIZE1
   1460 	if (size >= PMAP_MAPSIZE1)
   1461 		align = PMAP_MAPSIZE1;
   1462 
   1463 #ifdef PMAP_MAPSIZE2
   1464 
   1465 #if PMAP_MAPSIZE1 > PMAP_MAPSIZE2
   1466 #error PMAP_MAPSIZE1 must be smaller than PMAP_MAPSIZE2
   1467 #endif
   1468 
   1469 	if (size >= PMAP_MAPSIZE2)
   1470 		align = PMAP_MAPSIZE2;
   1471 
   1472 #ifdef PMAP_MAPSIZE3
   1473 
   1474 #if PMAP_MAPSIZE2 > PMAP_MAPSIZE3
   1475 #error PMAP_MAPSIZE2 must be smaller than PMAP_MAPSIZE3
   1476 #endif
   1477 
   1478 	if (size >= PMAP_MAPSIZE3)
   1479 		align = PMAP_MAPSIZE3;
   1480 #endif
   1481 #endif
   1482 #endif
   1483 
   1484 	va = uvm_km_alloc(kernel_map, size, align, kmflags);
   1485 	if (__predict_false(va == 0 && align > 0)) {
   1486 		align = 0;
   1487 		va = uvm_km_alloc(kernel_map, size, 0, kmflags);
   1488 	}
   1489 
   1490 	if (va == 0)
   1491 		return ENOMEM;
   1492 
   1493 	*kvap = (void *)va;
   1494 
   1495 	for (curseg = 0; curseg < nsegs; curseg++) {
   1496 		for (pa = segs[curseg].ds_addr;
   1497 		    pa < (segs[curseg].ds_addr + segs[curseg].ds_len);
   1498 		    pa += PAGE_SIZE, va += PAGE_SIZE, size -= PAGE_SIZE) {
   1499 			bool uncached = (flags & BUS_DMA_COHERENT);
   1500 			bool prefetchable = (flags & BUS_DMA_PREFETCHABLE);
   1501 #ifdef DEBUG_DMA
   1502 			printf("wiring P%#" PRIxPADDR
   1503 			    " to V%#" PRIxVADDR "\n", pa, va);
   1504 #endif	/* DEBUG_DMA */
   1505 			if (size == 0)
   1506 				panic("_bus_dmamem_map: size botch");
   1507 
   1508 			const struct riscv_dma_range * const dr =
   1509 			    _bus_dma_paddr_inrange(t->_ranges, t->_nranges, pa);
   1510 			/*
   1511 			 * If this dma region is coherent then there is
   1512 			 * no need for an uncached mapping.
   1513 			 */
   1514 			if (dr != NULL
   1515 			    && (dr->dr_flags & _BUS_DMAMAP_COHERENT)) {
   1516 				uncached = false;
   1517 			}
   1518 
   1519 			u_int pmap_flags = PMAP_WIRED;
   1520 			if (prefetchable)
   1521 				pmap_flags |= PMAP_WRITE_COMBINE;
   1522 			else if (uncached)
   1523 				pmap_flags |= PMAP_NOCACHE;
   1524 
   1525 			pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE,
   1526 			    pmap_flags);
   1527 		}
   1528 	}
   1529 	pmap_update(pmap_kernel());
   1530 #ifdef DEBUG_DMA
   1531 	printf("dmamem_map: =%p\n", *kvap);
   1532 #endif	/* DEBUG_DMA */
   1533 	return 0;
   1534 }
   1535 
   1536 /*
   1537  * Common function for unmapping DMA-safe memory.  May be called by
   1538  * bus-specific DMA memory unmapping functions.
   1539  */
   1540 void
   1541 _bus_dmamem_unmap(bus_dma_tag_t t, void *kva, size_t size)
   1542 {
   1543 
   1544 #ifdef DEBUG_DMA
   1545 	printf("dmamem_unmap: t=%p kva=%p size=%#zx\n", t, kva, size);
   1546 #endif	/* DEBUG_DMA */
   1547 	KASSERTMSG(((uintptr_t)kva & PAGE_MASK) == 0,
   1548 	    "kva %p (%#"PRIxPTR")", kva, ((uintptr_t)kva & PAGE_MASK));
   1549 
   1550 	/*
   1551 	 * Check to see if this used direct mapped memory.  If so we can
   1552 	 * just return since we have nothing to free up.
   1553 	 */
   1554 	if (pmap_md_direct_mapped_vaddr_p((vaddr_t)kva))
   1555 		return;
   1556 
   1557 	size = round_page(size);
   1558 	pmap_kremove((vaddr_t)kva, size);
   1559 	pmap_update(pmap_kernel());
   1560 	uvm_km_free(kernel_map, (vaddr_t)kva, size, UVM_KMF_VAONLY);
   1561 }
   1562 
   1563 /*
   1564  * Common function for mmap(2)'ing DMA-safe memory.  May be called by
   1565  * bus-specific DMA mmap(2)'ing functions.
   1566  */
   1567 paddr_t
   1568 _bus_dmamem_mmap(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs,
   1569     off_t off, int prot, int flags)
   1570 {
   1571 	/* Page not found. */
   1572 	return -1;
   1573 }
   1574 
   1575 /**********************************************************************
   1576  * DMA utility functions
   1577  **********************************************************************/
   1578 
   1579 /*
   1580  * Utility function to load a linear buffer.  lastaddrp holds state
   1581  * between invocations (for multiple-buffer loads).  segp contains
   1582  * the starting segment on entrance, and the ending segment on exit.
   1583  * first indicates if this is the first invocation of this function.
   1584  */
   1585 int
   1586 _bus_dmamap_load_buffer(bus_dma_tag_t t, bus_dmamap_t map, void *buf,
   1587     bus_size_t buflen, struct vmspace *vm, int flags)
   1588 {
   1589 	bus_size_t sgsize;
   1590 	bus_addr_t curaddr;
   1591 	vaddr_t vaddr = (vaddr_t)buf;
   1592 	int error;
   1593 	pmap_t pmap = vm_map_pmap(&vm->vm_map);
   1594 
   1595 #ifdef DEBUG_DMA
   1596 	printf("_bus_dmamap_load_buffer(buf=%p, len=%#" PRIxBUSSIZE
   1597 	    ", flags=%#x)\n", buf, buflen, flags);
   1598 #endif	/* DEBUG_DMA */
   1599 
   1600 
   1601 	while (buflen > 0) {
   1602 		/*
   1603 		 * Get the physical address for this segment.
   1604 		 */
   1605 		if (!pmap_extract(pmap, vaddr, &curaddr))
   1606 			return EFAULT;
   1607 
   1608 		KASSERTMSG((vaddr & PAGE_MASK) == (curaddr & PAGE_MASK),
   1609 		    "va %#" PRIxVADDR " curaddr %#" PRIxBUSADDR, vaddr, curaddr);
   1610 
   1611 		/*
   1612 		 * Compute the segment size, and adjust counts.
   1613 		 */
   1614 		sgsize = PAGE_SIZE - ((u_long)vaddr & PGOFSET);
   1615 		if (buflen < sgsize)
   1616 			sgsize = buflen;
   1617 
   1618 		error = _bus_dmamap_load_paddr(t, map, curaddr, sgsize,
   1619 		    false);
   1620 		if (__predict_false(error))
   1621 			return error;
   1622 
   1623 		vaddr += sgsize;
   1624 		buflen -= sgsize;
   1625 	}
   1626 
   1627 	return 0;
   1628 }
   1629 
   1630 /*
   1631  * Allocate physical memory from the given physical address range.
   1632  * Called by DMA-safe memory allocation methods.
   1633  */
   1634 int
   1635 _bus_dmamem_alloc_range(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment,
   1636     bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs,
   1637     int flags, paddr_t low, paddr_t high)
   1638 {
   1639 	paddr_t curaddr, lastaddr;
   1640 	struct vm_page *m;
   1641 	struct pglist mlist;
   1642 	int curseg, error;
   1643 
   1644 	KASSERTMSG(boundary == 0 || (boundary & (boundary - 1)) == 0,
   1645 	    "invalid boundary %#" PRIxBUSSIZE, boundary);
   1646 
   1647 #ifdef DEBUG_DMA
   1648 	printf("alloc_range: t=%p size=%#" PRIxBUSSIZE
   1649 	    " align=%#" PRIxBUSSIZE " boundary=%#" PRIxBUSSIZE
   1650 	    " segs=%p nsegs=%#x rsegs=%p flags=%#x"
   1651 	    " lo=%#" PRIxPADDR " hi=%#" PRIxPADDR "\n",
   1652 	    t, size, alignment, boundary, segs, nsegs, rsegs, flags, low, high);
   1653 #endif	/* DEBUG_DMA */
   1654 
   1655 	/* Always round the size. */
   1656 	size = round_page(size);
   1657 
   1658 	/*
   1659 	 * We accept boundaries < size, splitting in multiple segments
   1660 	 * if needed. uvm_pglistalloc does not, so compute an appropriate
   1661 	 * boundary: next power of 2 >= size
   1662 	 */
   1663 	bus_size_t uboundary = boundary;
   1664 	if (uboundary <= PAGE_SIZE) {
   1665 		uboundary = 0;
   1666 	} else {
   1667 		while (uboundary < size) {
   1668 			uboundary <<= 1;
   1669 		}
   1670 	}
   1671 
   1672 	/*
   1673 	 * Allocate pages from the VM system.
   1674 	 */
   1675 	error = uvm_pglistalloc(size, low, high, alignment, uboundary,
   1676 	    &mlist, nsegs, (flags & BUS_DMA_NOWAIT) == 0);
   1677 	if (error)
   1678 		return error;
   1679 
   1680 	/*
   1681 	 * Compute the location, size, and number of segments actually
   1682 	 * returned by the VM code.
   1683 	 */
   1684 	m = TAILQ_FIRST(&mlist);
   1685 	curseg = 0;
   1686 	lastaddr = segs[curseg].ds_addr = segs[curseg]._ds_paddr =
   1687 	    VM_PAGE_TO_PHYS(m);
   1688 	segs[curseg].ds_len = PAGE_SIZE;
   1689 #ifdef DEBUG_DMA
   1690 	printf("alloc: page %#" PRIxPADDR "\n", lastaddr);
   1691 #endif	/* DEBUG_DMA */
   1692 	m = TAILQ_NEXT(m, pageq.queue);
   1693 
   1694 	for (; m != NULL; m = TAILQ_NEXT(m, pageq.queue)) {
   1695 		curaddr = VM_PAGE_TO_PHYS(m);
   1696 		KASSERTMSG(low <= curaddr && curaddr < high,
   1697 		    "uvm_pglistalloc returned non-sensicaladdress %#" PRIxPADDR
   1698 		    "(low=%#" PRIxPADDR ", high=%#" PRIxPADDR "\n",
   1699 		    curaddr, low, high);
   1700 #ifdef DEBUG_DMA
   1701 		printf("alloc: page %#" PRIxPADDR "\n", curaddr);
   1702 #endif	/* DEBUG_DMA */
   1703 		if (curaddr == lastaddr + PAGE_SIZE
   1704 		    && (lastaddr & boundary) == (curaddr & boundary))
   1705 			segs[curseg].ds_len += PAGE_SIZE;
   1706 		else {
   1707 			curseg++;
   1708 			if (curseg >= nsegs) {
   1709 				uvm_pglistfree(&mlist);
   1710 				return EFBIG;
   1711 			}
   1712 			segs[curseg].ds_addr = curaddr;
   1713 			segs[curseg]._ds_paddr = curaddr;
   1714 			segs[curseg].ds_len = PAGE_SIZE;
   1715 		}
   1716 		lastaddr = curaddr;
   1717 	}
   1718 
   1719 	*rsegs = curseg + 1;
   1720 
   1721 	return 0;
   1722 }
   1723 
   1724 /*
   1725  * Check if a memory region intersects with a DMA range, and return the
   1726  * page-rounded intersection if it does.
   1727  */
   1728 int
   1729 riscv_dma_range_intersect(struct riscv_dma_range *ranges, int nranges,
   1730     paddr_t pa, psize_t size, paddr_t *pap, psize_t *sizep)
   1731 {
   1732 	struct riscv_dma_range *dr;
   1733 	int i;
   1734 
   1735 	if (ranges == NULL)
   1736 		return 0;
   1737 
   1738 	for (i = 0, dr = ranges; i < nranges; i++, dr++) {
   1739 		if (dr->dr_sysbase <= pa &&
   1740 		    pa < (dr->dr_sysbase + dr->dr_len)) {
   1741 			/*
   1742 			 * Beginning of region intersects with this range.
   1743 			 */
   1744 			*pap = trunc_page(pa);
   1745 			*sizep = round_page(uimin(pa + size,
   1746 			    dr->dr_sysbase + dr->dr_len) - pa);
   1747 			return 1;
   1748 		}
   1749 		if (pa < dr->dr_sysbase && dr->dr_sysbase < (pa + size)) {
   1750 			/*
   1751 			 * End of region intersects with this range.
   1752 			 */
   1753 			*pap = trunc_page(dr->dr_sysbase);
   1754 			*sizep = round_page(uimin((pa + size) - dr->dr_sysbase,
   1755 			    dr->dr_len));
   1756 			return 1;
   1757 		}
   1758 	}
   1759 
   1760 	/* No intersection found. */
   1761 	return 0;
   1762 }
   1763 
   1764 #ifdef _RISCV_NEED_BUS_DMA_BOUNCE
   1765 static int
   1766 _bus_dma_alloc_bouncebuf(bus_dma_tag_t t, bus_dmamap_t map,
   1767     bus_size_t size, int flags)
   1768 {
   1769 	struct riscv_bus_dma_cookie *cookie = map->_dm_cookie;
   1770 	int error = 0;
   1771 
   1772 	KASSERT(cookie != NULL);
   1773 
   1774 	cookie->id_bouncebuflen = round_page(size);
   1775 	error = _bus_dmamem_alloc(t, cookie->id_bouncebuflen,
   1776 	    PAGE_SIZE, map->_dm_boundary, cookie->id_bouncesegs,
   1777 	    map->_dm_segcnt, &cookie->id_nbouncesegs, flags);
   1778 	if (error == 0) {
   1779 		error = _bus_dmamem_map(t, cookie->id_bouncesegs,
   1780 		    cookie->id_nbouncesegs, cookie->id_bouncebuflen,
   1781 		    (void **)&cookie->id_bouncebuf, flags);
   1782 		if (error) {
   1783 			_bus_dmamem_free(t, cookie->id_bouncesegs,
   1784 			    cookie->id_nbouncesegs);
   1785 			cookie->id_bouncebuflen = 0;
   1786 			cookie->id_nbouncesegs = 0;
   1787 		} else {
   1788 			cookie->id_flags |= _BUS_DMA_HAS_BOUNCE;
   1789 		}
   1790 	} else {
   1791 		cookie->id_bouncebuflen = 0;
   1792 		cookie->id_nbouncesegs = 0;
   1793 	}
   1794 
   1795 	return error;
   1796 }
   1797 
   1798 static void
   1799 _bus_dma_free_bouncebuf(bus_dma_tag_t t, bus_dmamap_t map)
   1800 {
   1801 	struct riscv_bus_dma_cookie *cookie = map->_dm_cookie;
   1802 
   1803 	KASSERT(cookie != NULL);
   1804 
   1805 	_bus_dmamem_unmap(t, cookie->id_bouncebuf, cookie->id_bouncebuflen);
   1806 	_bus_dmamem_free(t, cookie->id_bouncesegs, cookie->id_nbouncesegs);
   1807 	cookie->id_bouncebuflen = 0;
   1808 	cookie->id_nbouncesegs = 0;
   1809 	cookie->id_flags &= ~_BUS_DMA_HAS_BOUNCE;
   1810 }
   1811 #endif /* _RISCV_NEED_BUS_DMA_BOUNCE */
   1812 
   1813 /*
   1814  * This function does the same as uiomove, but takes an explicit
   1815  * direction, and does not update the uio structure.
   1816  */
   1817 static int
   1818 _bus_dma_uiomove(void *buf, struct uio *uio, size_t n, int direction)
   1819 {
   1820 	struct iovec *iov;
   1821 	int error;
   1822 	struct vmspace *vm;
   1823 	char *cp;
   1824 	size_t resid, cnt;
   1825 	int i;
   1826 
   1827 	iov = uio->uio_iov;
   1828 	vm = uio->uio_vmspace;
   1829 	cp = buf;
   1830 	resid = n;
   1831 
   1832 	for (i = 0; i < uio->uio_iovcnt && resid > 0; i++) {
   1833 		iov = &uio->uio_iov[i];
   1834 		if (iov->iov_len == 0)
   1835 			continue;
   1836 		cnt = MIN(resid, iov->iov_len);
   1837 
   1838 		if (!VMSPACE_IS_KERNEL_P(vm)) {
   1839 			preempt_point();
   1840 		}
   1841 		if (direction == UIO_READ) {
   1842 			error = copyout_vmspace(vm, cp, iov->iov_base, cnt);
   1843 		} else {
   1844 			error = copyin_vmspace(vm, iov->iov_base, cp, cnt);
   1845 		}
   1846 		if (error)
   1847 			return error;
   1848 		cp += cnt;
   1849 		resid -= cnt;
   1850 	}
   1851 	return 0;
   1852 }
   1853 
   1854 int
   1855 _bus_dmatag_subregion(bus_dma_tag_t tag, bus_addr_t min_addr,
   1856     bus_addr_t max_addr, bus_dma_tag_t *newtag, int flags)
   1857 {
   1858 #ifdef _RISCV_NEED_BUS_DMA_BOUNCE
   1859 	if (min_addr >= max_addr)
   1860 		return EOPNOTSUPP;
   1861 
   1862 	struct riscv_dma_range *dr;
   1863 	bool psubset = true;
   1864 	size_t nranges = 0;
   1865 	size_t i;
   1866 	for (i = 0, dr = tag->_ranges; i < tag->_nranges; i++, dr++) {
   1867 		/*
   1868 		 * If the new {min,max}_addr are narrower than any of the
   1869 		 * ranges in the parent tag then we need a new tag;
   1870 		 * otherwise the parent tag is a subset of the new
   1871 		 * range and can continue to be used.
   1872 		 */
   1873 		if (min_addr > dr->dr_sysbase
   1874 		    || max_addr < dr->dr_sysbase + dr->dr_len - 1) {
   1875 			psubset = false;
   1876 		}
   1877 		if (min_addr <= dr->dr_sysbase + dr->dr_len
   1878 		    && max_addr >= dr->dr_sysbase) {
   1879 			nranges++;
   1880 		}
   1881 	}
   1882 	if (nranges == 0) {
   1883 		nranges = 1;
   1884 		psubset = false;
   1885 	}
   1886 	if (psubset) {
   1887 		*newtag = tag;
   1888 		/* if the tag must be freed, add a reference */
   1889 		if (tag->_tag_needs_free)
   1890 			(tag->_tag_needs_free)++;
   1891 		return 0;
   1892 	}
   1893 
   1894 	const size_t tagsize = sizeof(*tag) + nranges * sizeof(*dr);
   1895 	if ((*newtag = kmem_intr_zalloc(tagsize,
   1896 	    (flags & BUS_DMA_NOWAIT) ? KM_NOSLEEP : KM_SLEEP)) == NULL)
   1897 		return ENOMEM;
   1898 
   1899 	dr = (void *)(*newtag + 1);
   1900 	**newtag = *tag;
   1901 	(*newtag)->_tag_needs_free = 1;
   1902 	(*newtag)->_ranges = dr;
   1903 	(*newtag)->_nranges = nranges;
   1904 
   1905 	if (tag->_ranges == NULL) {
   1906 		dr->dr_sysbase = min_addr;
   1907 		dr->dr_busbase = min_addr;
   1908 		dr->dr_len = max_addr + 1 - min_addr;
   1909 	} else {
   1910 		struct riscv_dma_range *pdr;
   1911 
   1912 		for (i = 0, pdr = tag->_ranges; i < tag->_nranges; i++, pdr++) {
   1913 			KASSERT(nranges != 0);
   1914 
   1915 			if (min_addr > pdr->dr_sysbase + pdr->dr_len
   1916 			    || max_addr < pdr->dr_sysbase) {
   1917 				/*
   1918 				 * this range doesn't overlap with new limits,
   1919 				 * so skip.
   1920 				 */
   1921 				continue;
   1922 			}
   1923 			/*
   1924 			 * Copy the range and adjust to fit within the new
   1925 			 * limits
   1926 			 */
   1927 			dr[0] = pdr[0];
   1928 			if (dr->dr_sysbase < min_addr) {
   1929 				psize_t diff = min_addr - dr->dr_sysbase;
   1930 				dr->dr_busbase += diff;
   1931 				dr->dr_len -= diff;
   1932 				dr->dr_sysbase += diff;
   1933 			}
   1934 			if (max_addr <= dr->dr_sysbase + dr->dr_len - 1) {
   1935 				dr->dr_len = max_addr + 1 - dr->dr_sysbase;
   1936 			}
   1937 			dr++;
   1938 			nranges--;
   1939 		}
   1940 	}
   1941 
   1942 	return 0;
   1943 #else
   1944 	return EOPNOTSUPP;
   1945 #endif /* _RISCV_NEED_BUS_DMA_BOUNCE */
   1946 }
   1947 
   1948 void
   1949 _bus_dmatag_destroy(bus_dma_tag_t tag)
   1950 {
   1951 #ifdef _RISCV_NEED_BUS_DMA_BOUNCE
   1952 	switch (tag->_tag_needs_free) {
   1953 	case 0:
   1954 		break;				/* not allocated with kmem */
   1955 	case 1: {
   1956 		const size_t tagsize = sizeof(*tag)
   1957 		    + tag->_nranges * sizeof(*tag->_ranges);
   1958 		kmem_intr_free(tag, tagsize);	/* last reference to tag */
   1959 		break;
   1960 	}
   1961 	default:
   1962 		(tag->_tag_needs_free)--;	/* one less reference */
   1963 	}
   1964 #endif
   1965 }
   1966