| /src/sys/arch/arm/nxp/ |
| imx6_ccmvar.h | 171 #define CLK_FIXED_FACTOR(_name, _parent, _div, _mult) { \
174 .parent = (_parent), \
183 #define CLK_PFD(_name, _parent, _reg, _index) { \
186 .parent = (_parent), \
195 #define CLK_PLL(_name, _parent, _type, _reg, _mask, _powerdown, _ref) { \
198 .parent = (_parent), \
210 #define CLK_DIV(_name, _parent, _reg, _mask) { \
213 .parent = (_parent), \
224 #define CLK_DIV_BUSY(_name, _parent, _reg, _mask, _busy_reg, _busy_mask) { \
227 .parent = (_parent), \
[all...] |
| imx_ccm.h | 161 #define IMX_PLL(_id, _name, _parent, _reg, _div_mask, _flags) \
162 IMX_PLL_INDEX(_id, 0, _name, _parent, _reg, _div_mask, _flags)
163 #define IMX_PLL_INDEX(_id, _regidx, _name, _parent, _reg, _div_mask, _flags) \
170 .u.pll.parent = (_parent), \
209 #define IMX_FIXED_FACTOR(_id, _name, _parent, _mult, _div) \
215 .u.fixed_factor.parent = (_parent), \
268 #define IMX_DIV(_id, _name, _parent, _reg, _mask, _flags) \
269 IMX_DIV_INDEX(_id, 0, _name, _parent, _reg, _mask, _flags)
270 #define IMX_DIV_INDEX(_id, _regidx, _name, _parent, _reg, _mask, _flags) \
277 .u.div.parent = (_parent), \
[all...] |
| imx7d_ccm.c | 103 #define ANATOP_GATE(_id, _name, _parent, _reg, _mask) \
104 IMX_GATE_INDEX(_id, REGIDX_ANATOP, _name, _parent, _reg, _mask)
105 #define ANATOP_PLL(_id, _name, _parent, _reg, _div_mask, _flags) \
106 IMX_PLL_INDEX(_id, REGIDX_ANATOP, _name, _parent, _reg, _div_mask, _flags)
|
| /src/sys/arch/arm/ti/ |
| omap3_cm.c | 91 #define OMAP3_CM_HWMOD_CORE1(_name, _bit, _parent, _flags) \
92 TI_PRCM_HWMOD_MASK((_name), CM_CORE1_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))
93 #define OMAP3_CM_HWMOD_CORE3(_name, _bit, _parent, _flags) \
94 TI_PRCM_HWMOD_MASK((_name), CM_CORE3_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))
95 #define OMAP3_CM_HWMOD_WKUP(_name, _bit, _parent, _flags) \
96 TI_PRCM_HWMOD_MASK((_name), CM_WKUP_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))
97 #define OMAP3_CM_HWMOD_PER(_name, _bit, _parent, _flags) \
98 TI_PRCM_HWMOD_MASK((_name), CM_PER_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags))
99 #define OMAP3_CM_HWMOD_USBHOST(_name, _bit, _parent, _flags) \
100 TI_PRCM_HWMOD_MASK((_name), CM_USBHOST_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable, (_flags)
[all...] |
| ti_prcm.h | 126 #define TI_PRCM_FIXED_FACTOR(_name, _mult, _div, _parent) \
131 .u.fixed_factor.parent = (_parent), \
143 #define TI_PRCM_HWMOD(_name, _reg, _parent, _enable) \
144 TI_PRCM_HWMOD_MASK(_name, _reg, 0, _parent, _enable, 0)
146 #define TI_PRCM_HWMOD_MASK(_name, _reg, _mask, _parent, _enable, _flags) \
152 .u.hwmod.parent = (_parent), \
|
| am3_prcm.c | 129 #define AM3_PRCM_HWMOD_PER(_name, _reg, _parent) \
130 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable)
131 #define AM3_PRCM_HWMOD_PER_DISP(_name, _reg, _parent) \
132 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable_display)
133 #define AM3_PRCM_HWMOD_WKUP(_name, _reg, _parent) \
134 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_WKUP + (_reg), (_parent), am3_prcm_hwmod_enable)
|
| /src/sys/arch/arm/amlogic/ |
| meson_clk.h | 142 #define MESON_CLK_DIV(_id, _name, _parent, _reg, _div, _flags) \
147 .u.div.parent = (_parent), \
172 #define MESON_CLK_FIXED_FACTOR(_id, _name, _parent, _div, _mult) \
176 .u.fixed_factor.parent = (_parent), \
262 #define MESON_CLK_PLL_RATE(_id, _name, _parent, _enable, _m, _n, _frac, _l, \
267 .u.pll.parent = (_parent), \
280 #define MESON_CLK_PLL(_id, _name, _parent, _enable, _m, _n, _frac, _l, \
285 .u.pll.parent = (_parent), \
315 #define MESON_CLK_MPLL(_id, _name, _parent, _sdm, _sdm_enable, _n2, \
320 .u.mpll.parent = (_parent), \
[all...] |
| /src/sys/arch/riscv/starfive/ |
| jh71x0_clkc.h | 111 #define JH71X0CLKC_FIXED_FACTOR(_id, _name, _parent, _div, _mult) \
115 .jcc_ffactor.jcff_parent = (_parent), \
171 #define JH71X0CLKC_DIV_FLAGS(_id, _name, _maxdiv, _parent, _flags) \
179 .jcd_parent = (_parent), \
213 #define JH71X0CLKC_FRACDIV(_id, _name, _parent) \
221 .jcd_parent = (_parent), \
|
| /src/sys/arch/arm/nvidia/ |
| tegra210_car.c | 309 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \
311 .parent = (_parent), \
334 #define CLK_FIXED_DIV(_name, _parent, _div) { \
336 .parent = (_parent), \
344 #define CLK_DIV(_name, _parent, _reg, _bits) { \
346 .parent = (_parent), \
355 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \
358 .parent = (_parent), \
368 #define CLK_GATE_L(_name, _parent, _bits) \
369 CLK_GATE(_name, _parent, \
[all...] |
| tegra124_car.c | 297 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \
299 .parent = (_parent), \
322 #define CLK_FIXED_DIV(_name, _parent, _div) { \
324 .parent = (_parent), \
332 #define CLK_DIV(_name, _parent, _reg, _bits) { \
334 .parent = (_parent), \
343 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \
346 .parent = (_parent), \
356 #define CLK_GATE_L(_name, _parent, _bits) \
357 CLK_GATE(_name, _parent, \
[all...] |
| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu.h | 129 #define SUNXI_CCU_NKMP_TABLE(_id, _name, _parent, _reg, _n, _k, _m, \
135 .u.nkmp.parent = (_parent), \
150 #define SUNXI_CCU_NKMP(_id, _name, _parent, _reg, _n, _k, _m, \
152 SUNXI_CCU_NKMP_TABLE(_id, _name, _parent, _reg, _n, _k, _m, \
326 #define SUNXI_CCU_PHASE(_id, _name, _parent, _reg, _mask) \
331 .u.phase.parent = (_parent), \
351 #define SUNXI_CCU_FIXED_FACTOR(_id, _name, _parent, _div, _mult) \
355 .u.fixed_factor.parent = (_parent), \
391 #define SUNXI_CCU_FRACTIONAL(_id, _name, _parent, _reg, _m, _m_min, _m_max, \
398 .u.fractional.parent = (_parent), \
[all...] |
| /src/sys/arch/arm/rockchip/ |
| rk_cru.h | 327 #define RK_COMPOSITE_NOMUX(_id, _name, _parent, _div_reg, _div_mask, _gate_reg, _gate_mask, _flags) \
328 _RK_COMPOSITE_INIT(_id, _name, (const char *[]){ _parent }, _div_reg, 0, _div_mask, _gate_reg, _gate_mask, 0, _flags)
336 #define RK_COMPOSITE_FRAC(_id, _name, _parent, _frac_reg, _flags) \
337 _RK_COMPOSITE_INIT(_id, _name, (const char *[]){ _parent }, 0, 0, 0, 0, 0, _frac_reg, (_flags) | RK_COMPOSITE_FRACDIV)
339 #define RK_DIV(_id, _name, _parent, _div_reg, _div_mask, _flags) \
340 _RK_COMPOSITE_INIT(_id, _name, (const char *[]){ _parent }, _div_reg, 0, _div_mask, 0, 0, 0, _flags)
|
| /src/sys/arch/arm/samsung/ |
| exynos5410_clock.c | 136 #define CLK_PLL(_name, _parent, _lock, _con0) { \
138 .parent = (_parent), \
167 #define CLK_DIVF(_name, _parent, _reg, _bits, _f) { \
170 .parent = (_parent), \
179 #define CLK_DIV(_name, _parent, _reg, _bits) \
180 CLK_DIVF(_name, _parent, _reg, _bits, 0)
182 #define CLK_GATE(_name, _parent, _reg, _bits, _f) { \
185 .parent = (_parent), \
|
| exynos5422_clock.c | 280 #define CLK_PLL(_name, _parent, _lock, _con0) { \
282 .parent = (_parent), \
311 #define CLK_DIV(_name, _parent, _reg, _bits) { \
313 .parent = (_parent), \
322 #define CLK_GATE(_name, _parent, _reg, _bits, _f) { \
325 .parent = (_parent), \
|
| /src/sys/arch/sparc64/include/ |
| bus_defs.h | 235 struct sparc_bus_dma_tag* _parent; member in struct:sparc_bus_dma_tag
|
| /src/sys/arch/sparc64/dev/ |
| iommu.c | 753 bus_dmamap_unload(t->_parent, map);
762 bus_dmamap_unload(t->_parent, map);
1183 bus_dmamap_sync(t->_parent, map, offset, len, ops);
1189 bus_dmamap_sync(t->_parent, map, offset, len, ops);
1203 return (bus_dmamem_alloc(t->_parent, size, alignment, boundary,
1213 bus_dmamem_free(t->_parent, segs, nsegs);
|
| pyro.c | 420 dt->_parent = pdt;
464 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz,
|
| vpci.c | 443 dt->_parent = pdt;
487 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz,
|
| sbus.c | 593 sdt->_parent = psdt;
621 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz,
|
| psycho.c | 1103 dt->_parent = pdt;
1518 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz,
1547 bus_dmamap_sync(t->_parent, map, offset, len, ops);
|
| schizo.c | 651 dt->_parent = pdt;
695 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz,
|
