| /src/common/lib/libc/arch/sparc/net/ |
| htons.S | 51 andn %o0, %o1, %o0
|
| ntohs.S | 52 andn %o0, %o1, %o0
|
| /src/common/lib/libc/arch/sparc64/net/ |
| htons.S | 52 andn %o0, %o1, %o0
|
| ntohs.S | 53 andn %o0, %o1, %o0
|
| /src/lib/csu/arch/sparc/ |
| crt0.S | 50 andn %sp, 7, %sp ! align stack
|
| /src/lib/libc/compat/arch/sparc64/sys/ |
| compat___sigtramp1.S | 113 andn %l0, BLOCK_ALIGN, %l0 /* we can do a block store */
120 andn %l0, BLOCK_ALIGN, %l0 /* we can do a block store */
145 andn %l0, BLOCK_ALIGN, %l0 /* we can do a block load */
153 andn %l0, BLOCK_ALIGN, %l0 /* we can do a block load */
|
| /src/lib/libc/arch/sparc/gen/ |
| modf.S | 104 andn %i0, %l1, %l0
135 andn %l5, %l3, %l6
149 andn %l6, %l3, %l6 ! %l6 = %fsr & ~FSR_RD;
|
| /src/lib/libc/arch/sparc64/gen/ |
| modf.S | 130 andn %l5, %l3, %l6
144 andn %l6, %l3, %l6 ! %l6 = %fsr & ~FSR_RD;
|
| /src/common/lib/libc/arch/sparc64/string/ |
| strlen.S | 68 andn %o0, 0x7, %o1
115 or %g1, %o2, %o5 ! Do step 1 -- use or/andn instead of nor/and
|
| strmacros.h | 56 andn %l0, BLOCK_ALIGN, %l0; /* Align it */ \
|
| memcpy.S | 192 andn %l0, 7, %l0 ! Source addr
552 andn %o0, 7, %o3 ! Start of block
556 andn %o5, BLOCK_ALIGN, %o5 ! Last safe addr.
|
| /src/sys/arch/sparc/sparc/ |
| lock_stubs.s | 136 andn %o1, PSR_PIL, %o1
178 andn %o1, PSR_PIL, %o1
|
| locore.s | 1250 be,a 1f; andn addr, page_offset, pte; \
1253 andn addr, page_offset, pte; \
1260 andn pte, (PG_W >> PG_PROTSHIFT), pte; \
1276 andn addr, page_offset, pte
1912 andn %o0, IE_ALLIE, %o0
2492 andn %l5, %l4, %l5 ! clear soft intr bit
2503 andn %l0, PSR_PIL, %l4 ! %l4 = psr & ~PSR_PIL |
2533 andn %o3, PSR_PIL, %o3 ! %o3 = psr & ~PSR_PIL
2639 andn %l0, PSR_PIL, %l4 ! %l4 = psr & ~PSR_PIL |
2688 andn %l0, PSR_PIL, %l4 ! %l4 = psr & ~PSR_PIL
4926 \/*3*\/ andn %g2, %o0, %g2 ! newpsr &= ~(PSR_EF|PSR_EC|PSR_PIL); label
[all...] |
| bsd_fdintr.s | 86 andn %l7, AUXIO4C_FTC, %l7; \
|
| /src/sys/arch/sparc64/include/ |
| locore.h | 55 andn a, 0x3f, t; \
|
| /src/sys/arch/sparc/stand/ofwboot/ |
| srt0.s | 79 andn %sp, 0x0f, %sp ! 16 byte align, per ELF spec.
93 andn %g1, 0x7, %g1
|
| /src/sys/arch/sparc/stand/common/ |
| srt0.S | 135 andn %o0, PSR_PIL, %o0
|
| /src/sys/arch/sparc64/sparc64/ |
| bsd_fdintr.s | 161 andn %l7, AUXIO_LED_FTC, %l7
|
| locore.s | 1515 andn %g1, %g4, %g4; /* Are we out of the interrupt stack range? */ \
1814 andn %g3, 0xfff, %g6
1976 andn %g7, 0x3f, %g5 ! window fill traps are all 0b 0000 11xx xxxx
2447 andn %g2, CWP, %g2
3382 andn %g2, 0x00f, %g3
3417 andn %g3, TSTATE_CWP, %g3
3653 andn %g7, 0x3f, %g5
4995 andn %g1, CWP, %g1
5304 andn %g1, CWP, %g1 ! Clear it from %tstate
5466 andn %l1, %l4, %l1 ! Mask the phys page numbe
[all...] |
| mp_subr.S | 169 andn %g2, 0xfff, %g2 ! drop unused va bits
468 andn %g1, 3, %g1 ! Now we have bits <29:2> set
|
