| /src/sys/arch/ibmnws/ibmnws/ |
| machdep.c | 91 uint32_t sa, ea, banks; local in function:initppc
108 /* Which memory banks are enabled? */
110 banks = in32rb(PCI_MODE1_DATA_REG) & 0xFF;
115 if (banks & IBM_82660_MEM_BANK0_ENABLED)
118 if (banks & IBM_82660_MEM_BANK1_ENABLED)
121 if (banks & IBM_82660_MEM_BANK2_ENABLED)
124 if (banks & IBM_82660_MEM_BANK3_ENABLED)
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| /src/sys/arch/arm/rockchip/ |
| rk3399_iomux.c | 175 const struct rk3399_iomux_bank *banks; member in struct:rk3399_iomux_conf
180 .banks = rk3399_iomux_banks,
214 const struct rk3399_iomux_bank *banks = sc->sc_conf->banks; local in function:rk3399_iomux_set_bias
220 struct syscon * const syscon = sc->sc_syscon[banks[bank].regs];
228 const int pull_type = banks[bank].iomux[idx / 8].pull_type;
268 const struct rk3399_iomux_bank *banks = sc->sc_conf->banks; local in function:rk3399_iomux_set_drive_strength
277 const int drv = rk3399_iomux_map_drive_strength(sc, banks[bank].iomux[idx / 8].drv_type, val);
281 struct syscon * const syscon = sc->sc_syscon[banks[bank].regs]
358 const struct rk3399_iomux_bank *banks = sc->sc_conf->banks; local in function:rk3399_iomux_set_mux
414 const struct rk3399_iomux_bank *banks = sc->sc_conf->banks; local in function:rk3399_iomux_pinctrl_set_config
[all...] |
| rk3328_iomux.c | 108 const struct rk3328_iomux_bank *banks; member in struct:rk3328_iomux_conf
113 .banks = rk3328_iomux_banks,
147 const struct rk3328_iomux_bank *banks = sc->sc_conf->banks; local in function:rk3328_iomux_calc_iomux_reg
151 *reg = banks[bank].iomux[pin / 8].base;
152 if (banks[bank].iomux[pin / 8].type & RK3328_IOMUX_TYPE_3BIT) {
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| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/ |
| stingray-board-base.dtsi | 22 &memory { /* Default DRAM banks */
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| /src/games/trek/ |
| phaser.c | 59 ** There are up to NBANKS phaser banks which may be fired
85 struct banks { struct
102 struct banks *b;
108 struct banks bank[NBANKS];
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| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| s3c2416-pinctrl.dtsi | 12 * Pin banks
|
| bcm283x.dtsi | 111 * The GPIO IP block is designed for 3 banks of GPIOs.
115 * Since the BCM2835 only has 2 banks, the 2nd bank
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| s3c64xx-pinctrl.dtsi | 8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
16 * Pin banks
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| meson8.dtsi | 471 gpio: banks@80b0 {
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| meson8b.dtsi | 425 gpio: banks@80b0 {
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| /src/sys/arch/mips/sibyte/include/ |
| bcm1480_regs.h | 181 #define A_BCM1480_L2_WAY_ENABLE(A, banks) (A | (((~(banks))&0x0F) << 8))
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| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| nouveau_nvkm_subdev_fb_ramnv50.c | 513 int colbits, rowbitsa, rowbitsb, banks; local in function:nv50_fb_vram_rblock
526 banks = 1 << (((r4 & 0x03000000) >> 24) + 2);
528 rowsize = ram->parts * banks * (1 << colbits) * 8;
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| /src/sys/arch/mac68k/mac68k/ |
| locore.s | 359 | now configure banks 2 & 3
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| /src/sys/dev/pci/cxgb/ |
| cxgb_t3_hw.c | 3574 unsigned int banks = !!(cfg & F_BKS) + 1; local in function:mc7_calc_size
3577 unsigned int MBs = ((256 << density) * banks) / (org << width);
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