| /src/sys/arch/arm/arm/ |
| cpufunc_asm_armv6.S | 53 mcrne p15, 0, r0, c7, c14, 0 /* clean and invalidate D cache */
103 mcrr p15, 0, r1, r0, c14 /* clean and invalidate D cache range */
127 mcrr p15, 0, r1, r0, c14 /* clean & invalidate D cache range */
144 mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */
|
| cpufunc_asm_arm11x6.S | 102 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
107 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
195 mcrr p15, 0, r1, r0, c14 /* clean and invalidate D cache range */
|
| cpufunc_asm_arm9.S | 156 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
195 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
219 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
223 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
|
| cpufunc_asm_armv5.S | 145 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
186 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
210 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
214 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
|
| cpufunc_asm_armv5_ec.S | 65 2: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
147 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
188 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
207 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
|
| cpufunc_asm_sheeva.S | 108 mcr p15, 5, r0, c15, c14, 0 /* Inv zone start address */
109 mcr p15, 5, r2, c15, c14, 1 /* Inv zone end address */
|
| armv6_start.S | 696 mcrr p15, 4, r1, r1, c14
1046 mcr p15, 0, r0, c7, c14, 0 /* Clean and Invalidate Entire Data Cache */
|
| cpufunc_asm_armv7.S | 255 mcr p15, 0, r0, c7, c14, 1 @ wb and inv the D-Cache line to PoC
301 mcr p15, 0, r0, c7, c14, 1 @ wb and inv the D-Cache line
509 1: mcr p15, 0, r3, c7, c14, 2 @ DCCISW (data cache clean and invalidate by set/way)
|
| /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.trace/ |
| collection.c | 65 c8, c9, c10, c11, c12, c13, c14, c15, cminus; variable
257 l14 = s14 = c14 = 14; l15 = s15 = c15 = 15;
308 l14 = s14 = c14 = 0; l15 = s15 = c15 = 0;
|
| /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.trace/ |
| collection.c | 65 c8, c9, c10, c11, c12, c13, c14, c15, cminus; variable
257 l14 = s14 = c14 = 14; l15 = s15 = c15 = 15;
308 l14 = s14 = c14 = 0; l15 = s15 = c15 = 0;
|
| /src/external/gpl3/binutils/dist/include/opcode/ |
| crx.h | 69 c9, c10, c11, c12, c13, c14, c15, enumerator in enum:__anon10637
|
| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| crx.h | 69 c9, c10, c11, c12, c13, c14, c15, enumerator in enum:__anon12101
|
| /src/external/gpl3/gdb.old/dist/include/opcode/ |
| crx.h | 69 c9, c10, c11, c12, c13, c14, c15, enumerator in enum:__anon21489
|
| /src/external/gpl3/gdb/dist/include/opcode/ |
| crx.h | 69 c9, c10, c11, c12, c13, c14, c15, enumerator in enum:__anon1077
|
| /src/crypto/external/apache2/openssl/dist/crypto/ |
| armv4cpuid.pl | 159 mrrc p15,0,r0,r1,c14 @ CNTPCT
161 mrrc p15,1,r0,r1,c14 @ CNTVCT
|
| /src/crypto/external/apache2/openssl/lib/libcrypto/arch/arm/ |
| armv4cpuid.S | 136 mrrc p15,0,r0,r1,c14 @ CNTPCT
138 mrrc p15,1,r0,r1,c14 @ CNTVCT
|
| /src/crypto/external/bsd/openssl/dist/crypto/ |
| armv4cpuid.pl | 159 mrrc p15,0,r0,r1,c14 @ CNTPCT
161 mrrc p15,1,r0,r1,c14 @ CNTVCT
|
| /src/crypto/external/bsd/openssl/lib/libcrypto/arch/arm/ |
| armv4cpuid.S | 136 mrrc p15,0,r0,r1,c14 @ CNTPCT
138 mrrc p15,1,r0,r1,c14 @ CNTVCT
|
| /src/crypto/external/bsd/openssl.old/dist/crypto/ |
| armv4cpuid.pl | 155 mrrc p15,0,r0,r1,c14 @ CNTPCT
157 mrrc p15,1,r0,r1,c14 @ CNTVCT
|
| /src/crypto/external/bsd/openssl.old/lib/libcrypto/arch/arm/ |
| armv4cpuid.S | 135 mrrc p15,0,r0,r1,c14 @ CNTPCT
137 mrrc p15,1,r0,r1,c14 @ CNTVCT
|
| /src/sys/stand/efiboot/bootarm/ |
| cache.S | 48 mcr p15, 0, r0, c7, c14, 1 @ wb and inv the D-Cache line to PoC
92 1: mcr p15, 0, r3, c7, c14, 2 @ DCCISW (data cache clean and invalidate by set/way)
|
| /src/sys/arch/evbarm/gemini/ |
| gemini_start.S | 197 mcr p15, 0, r0, c7, c14, 0 /* Clean & Invalidate Entire D cache */
|
| /src/external/gpl3/gcc/dist/gcc/ |
| edit-context.cc | 1745 location_t c14 = linemap_position_for_column (line_table, 14); local
1789 source_range range = source_range::from_locations (c11, c14);
1798 if (c14 <= LINE_MAP_MAX_LOCATION_WITH_COLS)
|
| input.cc | 2220 const location_t c14 = linemap_position_for_column (line_table, 14); local
2228 const location_t aaa = make_location (c13, c12, c14);
2232 ASSERT_EQ (c14, get_finish (aaa));
2236 const location_t not_aaa = make_location (c11, aaa, c14);
2242 ASSERT_EQ (c14, get_finish (not_aaa));
|
| /src/external/gpl3/gcc.old/dist/gcc/ |
| edit-context.cc | 1715 location_t c14 = linemap_position_for_column (line_table, 14); local
1757 source_range range = source_range::from_locations (c11, c14);
1765 if (c14 <= LINE_MAP_MAX_LOCATION_WITH_COLS)
|
