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    Searched refs:c14 (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/arch/arm/arm/
cpufunc_asm_armv6.S 53 mcrne p15, 0, r0, c7, c14, 0 /* clean and invalidate D cache */
103 mcrr p15, 0, r1, r0, c14 /* clean and invalidate D cache range */
127 mcrr p15, 0, r1, r0, c14 /* clean & invalidate D cache range */
144 mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */
cpufunc_asm_arm11x6.S 105 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
110 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
198 mcrr p15, 0, r1, r0, c14 /* clean and invalidate D cache range */
cpufunc_asm_armv5_ec.S 65 2: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
147 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
188 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
207 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
cpufunc_asm_arm9.S 156 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
195 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
219 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
223 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
cpufunc_asm_armv5.S 145 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
186 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
210 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
214 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
cpufunc_asm_sheeva.S 108 mcr p15, 5, r0, c15, c14, 0 /* Inv zone start address */
109 mcr p15, 5, r2, c15, c14, 1 /* Inv zone end address */
cpufunc_asm_armv7.S 255 mcr p15, 0, r0, c7, c14, 1 @ wb and inv the D-Cache line to PoC
301 mcr p15, 0, r0, c7, c14, 1 @ wb and inv the D-Cache line
509 1: mcr p15, 0, r3, c7, c14, 2 @ DCCISW (data cache clean and invalidate by set/way)
armv6_start.S 696 mcrr p15, 4, r1, r1, c14
1046 mcr p15, 0, r0, c7, c14, 0 /* Clean and Invalidate Entire Data Cache */
  /src/sys/stand/efiboot/bootarm/
cache.S 48 mcr p15, 0, r0, c7, c14, 1 @ wb and inv the D-Cache line to PoC
92 1: mcr p15, 0, r3, c7, c14, 2 @ DCCISW (data cache clean and invalidate by set/way)
  /src/sys/arch/evbarm/gemini/
gemini_start.S 200 mcr p15, 0, r0, c7, c14, 0 /* Clean & Invalidate Entire D cache */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
berlin2.dtsi 265 timer1: timer@2c14 {
berlin2cd.dtsi 309 timer1: timer@2c14 {
berlin2q.dtsi 349 timer1: timer@2c14 {
aspeed-bmc-ibm-everest.dts 2054 label = "cpu0-c14";
  /src/sys/arch/m68k/060sp/dist/
fplsp.sa 736 dc.l $600661ff,$00004c14,$4cee0303,$ff9cf22e

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