| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_cdclk.c | 35 * DOC: CDCLK / RAWCLK
40 * are the core display clock (CDCLK) and RAWCLK.
42 * CDCLK clocks most of the display pipe logic, and thus its frequency
47 * On several platforms the CDCLK frequency can be changed dynamically
49 * Typically changes to the CDCLK frequency require all the display pipes
52 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
53 * DMC will not change the active CDCLK frequency however, so that part
65 cdclk_state->cdclk = 133333;
71 cdclk_state->cdclk = 200000;
77 cdclk_state->cdclk = 266667
535 int cdclk = cdclk_state->cdclk; local in function:vlv_set_cdclk
622 int cdclk = cdclk_state->cdclk; local in function:chv_set_cdclk
723 int cdclk = cdclk_state->cdclk; local in function:bdw_set_cdclk
1000 int cdclk = cdclk_state->cdclk; local in function:skl_set_cdclk
1499 int cdclk = cdclk_state->cdclk; local in function:bxt_set_cdclk
1614 int cdclk, vco; local in function:bxt_sanitize_cdclk
2122 int min_cdclk, cdclk; local in function:vlv_modeset_calc_cdclk
2149 int min_cdclk, cdclk; local in function:bdw_modeset_calc_cdclk
2216 int min_cdclk, cdclk, vco; local in function:skl_modeset_calc_cdclk
2252 int min_cdclk, min_voltage_level, cdclk, vco; local in function:bxt_modeset_calc_cdclk
[all...] |
| intel_cdclk.h | 22 u32 cdclk; member in struct:intel_cdclk_vals
|
| intel_atomic.c | 513 memset(&state->cdclk.logical, 0, sizeof(state->cdclk.logical));
514 memset(&state->cdclk.actual, 0, sizeof(state->cdclk.actual));
515 state->cdclk.pipe = INVALID_PIPE;
|
| intel_atomic_plane.c | 181 * Does the cdclk need to be bumbed up?
184 * cdclk frequency is calculated so state->cdclk.logical
186 * cdclk state under dev_priv->cdclk.logical. This is
190 if (crtc_state->min_cdclk[plane->id] > dev_priv->cdclk.logical.cdclk) {
191 DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk (%d kHz) > logical cdclk (%d kHz)\n",
194 dev_priv->cdclk.logical.cdclk);
[all...] |
| intel_audio.c | 825 to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true;
826 to_intel_atomic_state(state)->cdclk.force_min_cdclk =
829 /* Protects dev_priv->cdclk.force_min_cdclk */
865 /* Force CDCLK to 2*BCLK as long as we need audio powered. */
883 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
922 /* Get CDCLK in kHz */
930 return dev_priv->cdclk.hw.cdclk;
|
| intel_dpll_mgr.c | 1108 /* DPLL0 is always enabled since it drives CDCLK */
2067 * Note: DVFS is actually handled via the cdclk code paths,
2085 * Note: DVFS is actually handled via the cdclk code paths,
2111 * Note: DVFS is actually handled via the cdclk code paths,
2129 * Note: DVFS is actually handled via the cdclk code paths,
2268 int ref_clock = dev_priv->cdclk.hw.ref;
2565 dev_priv->cdclk.hw.ref == 24000 ?
2588 switch (dev_priv->cdclk.hw.ref) {
2590 MISSING_CASE(dev_priv->cdclk.hw.ref);
2601 switch (dev_priv->cdclk.hw.ref)
[all...] |
| intel_fbc.c | 761 cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
|
| intel_panel.c | 1488 clock = KHz(dev_priv->cdclk.hw.cdclk);
1506 clock = KHz(dev_priv->cdclk.hw.cdclk);
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| intel_display.c | 4047 * of cdclk when the sprite plane is enabled on the
4049 * never allowed to exceed 80% of cdclk. Let's just go
7776 * the increased cdclk requirement into account when
7777 * calculating the new cdclk.
7779 * Should measure whether using a lower cdclk w/o IPS
7811 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
7813 crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100)
14302 if (!state->cdclk.force_min_cdclk_changed)
14303 state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk
[all...] |
| intel_display_types.h | 466 * Logical state of cdclk (used for all scaling, watermark,
473 * Actual state of cdclk, can be different from the logical
482 } cdclk; member in struct:intel_atomic_state
497 /* minimum acceptable cdclk for each pipe */
516 * cdclk.*
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| intel_display_power.c | 1060 WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
4504 DRM_ERROR("CDCLK source is not LCPLL\n");
4676 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
5013 /* 4. Enable CDCLK. */
|
| intel_dp.c | 1250 * The clock divider is based off the cdclk or PCH rawclk, and would
1251 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
1255 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1281 * derive the clock from CDCLK automatically). We still implement the
|
| intel_ddi.c | 1461 ref_clock = dev_priv->cdclk.hw.ref;
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| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| s3c64xx-pinctrl.dtsi | 334 i2s0_cdclk: i2s0-cdclk {
346 i2s1_cdclk: i2s1-cdclk {
360 i2s2_cdclk: i2s2-cdclk {
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| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| debugfs_gt_pm.c | 460 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk);
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| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_drv.h | 288 u8 (*calc_voltage_level)(int cdclk);
895 unsigned int cdclk, vco, ref, bypass; member in struct:intel_cdclk_state
1036 * The current logical cdclk state.
1037 * See intel_atomic_state.cdclk.logical
1041 * The current actual cdclk state.
1042 * See intel_atomic_state.cdclk.actual
1045 /* The current hardware cdclk state */
1048 /* cdclk, divider, and ratio table from bspec */
1052 } cdclk; member in struct:drm_i915_private
1098 /* dpll and cdclk state is protected by connection_mutex *
[all...] |
| intel_pm.c | 2835 if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
2844 intel_state->cdclk.logical.cdclk);
|
| i915_debugfs.c | 1004 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
|
