HomeSort by: relevance | last modified time | path
    Searched refs:cgs_read_ind_register (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/
cgs_common.h 105 * cgs_read_ind_register() - Read an indirect register
137 cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
172 #define cgs_read_ind_register(dev,space,index) \ macro
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
smu_helper.h 144 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
148 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
157 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
162 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
amdgpu_smu8_hwmgr.c 1529 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
1541 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
1664 uint32_t val = cgs_read_ind_register(hwmgr->device,
1690 uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
1692 uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1694 uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1715 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
1721 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
amdgpu_vega10_powertune.c 813 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
819 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset);
825 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset);
896 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL);
903 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL);
910 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL);
917 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL);
924 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL);
amdgpu_smu7_hwmgr.c 161 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
397 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
524 tmp = (cgs_read_ind_register(hwmgr->device,
1065 soft_register_value = cgs_read_ind_register(hwmgr->device,
1081 soft_register_value = cgs_read_ind_register(hwmgr->device,
2164 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3521 tmp = cgs_read_ind_register(hwmgr->device,
3564 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
4078 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4288 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
    [all...]
amdgpu_smu7_powertune.c 915 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset);
919 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
923 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dm_services.h 96 return cgs_read_ind_register(ctx->cgs_device, addr_space, index);
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 1686 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1688 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1745 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1818 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
2385 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2420 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2586 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2600 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2621 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2635 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset))
    [all...]
amdgpu_tonga_smumgr.c 1602 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1604 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1671 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1742 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2696 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2730 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
3185 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
3199 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
3220 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
3234 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset))
    [all...]
amdgpu_polaris10_smumgr.c 331 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
1532 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1593 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
2197 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2232 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2502 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2516 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2537 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2551 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
amdgpu_smu7_smumgr.c 168 && (0x20100 <= cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
amdgpu_vegam_smumgr.c 351 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
386 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
1543 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1554 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
amdgpu_ci_smumgr.c 195 && (0x20100 <= cgs_read_ind_register(hwmgr->device,
2797 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2811 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2832 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2846 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
amdgpu_iceland_smumgr.c 216 val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,

Completed in 49 milliseconds