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    Searched refs:ch_channel (Results 1 - 25 of 78) sorted by relevancy

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  /src/sys/dev/pci/
rdcide.c 219 psd1atr &= ~RDCIDE_PSD1ATR_SETUP_MASK(chp->ch_channel);
220 psd1atr &= ~RDCIDE_PSD1ATR_HOLD_MASK(chp->ch_channel);
222 udccr &= ~RDCIDE_UDCCR_EN(chp->ch_channel, drive);
223 udccr &= ~RDCIDE_UDCCR_TIM_MASK(chp->ch_channel, drive);
224 iiocr &= ~RDCIDE_IIOCR_CLK_MASK(chp->ch_channel, drive);
231 patr |= RDCIDE_PATR_ATA(chp->ch_channel, drive);
235 chp->ch_channel);
238 chp->ch_channel);
240 patr |= RDCIDE_PATR_DEV1_TEN(chp->ch_channel);
243 chp->ch_channel);
    [all...]
svwsata.c 256 (wdc_cp->ch_channel << 8) + SVWSATA_TF0,
265 (wdc_cp->ch_channel << 8) + SVWSATA_TF8, 4,
291 (wdc_cp->ch_channel << 8) + SVWSATA_SSTATUS, 1,
295 wdc_cp->ch_channel);
299 (wdc_cp->ch_channel << 8) + SVWSATA_SERROR, 1,
303 wdc_cp->ch_channel);
307 (wdc_cp->ch_channel << 8) + SVWSATA_SCONTROL, 1,
311 wdc_cp->ch_channel);
316 (wdc_cp->ch_channel << 8) + SVWSATA_SICR1,
318 (wdc_cp->ch_channel << 8) + SVWSATA_SICR1
    [all...]
viaide.c 773 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) {
781 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel);
783 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel);
814 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel,
847 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel);
848 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel);
870 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) |
871 APO_UDMA_EN_MTH(chp->ch_channel, drive);
877 chp->ch_channel,
883 chp->ch_channel,
    [all...]
cmdide.c 154 cp->ata_channel.ch_channel = channel;
197 CMDIDE_ACT_CHANNEL_NONE, chp->ch_channel)
207 ochp->ch_channel, CMDIDE_ACT_CHANNEL_NONE);
210 KASSERT(oact == ochp->ch_channel);
418 sc->sc_tag, CMD_UDMATIM(chp->ch_channel));
422 CMD_BICSR_80(chp->ch_channel)) == 0)
435 CMD_UDMATIM(chp->ch_channel), udma_reg);
446 CMD_UDMATIM(chp->ch_channel));
449 CMD_UDMATIM(chp->ch_channel),
461 CMD_DATA_TIM(chp->ch_channel, drive), tim)
    [all...]
ixpide.c 198 IXP_UDMA_ENABLE(udma, chp->ch_channel, drive);
199 IXP_SET_MODE(udma, chp->ch_channel, drive, drvp->UDMA_mode);
201 IXP_UDMA_DISABLE(udma, chp->ch_channel, drive);
202 IXP_SET_TIMING(mdma_timing, chp->ch_channel, drive,
205 IXP_UDMA_DISABLE(udma, chp->ch_channel, drive);
214 IXP_SET_MODE(pio, chp->ch_channel, drive, drvp->PIO_mode);
215 IXP_SET_TIMING(pio_timing, chp->ch_channel, drive,
aceride.c 246 ACER_PCIB_CTRL, reg & ~ACER_PCIB_CTRL_ENCHAN(chp->ch_channel));
272 ACER_0x4A_80PIN(chp->ch_channel)) {
286 "channel %d drive %d 0x%x\n", chp->ch_channel, drive,
288 ACER_IDETIM(chp->ch_channel, drive))), DEBUG_PROBE);
290 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->ch_channel, drive, 0x3) |
291 ACER_UDMA_EN(chp->ch_channel, drive) |
292 ACER_UDMA_TIM(chp->ch_channel, drive, 0x7));
305 ACER_FTH_OPL(chp->ch_channel, drive, 0x1);
309 acer_fifo_udma |= ACER_FTH_OPL(chp->ch_channel, drive, 0x2);
315 acer_fifo_udma |= ACER_UDMA_EN(chp->ch_channel, drive)
    [all...]
satalink.c 600 cp->ata_channel.ch_channel = channel;
619 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF0,
628 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF8,
809 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol);
812 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol);
815 sstatus = BA5_READ_4(sc, chp->ch_channel, ba5_SStatus);
819 chp->ch_channel, sstatus,
820 BA5_READ_4(sc, chp->ch_channel, ba5_SControl));
830 "communication not established\n", chp->ch_channel);
835 "port %d: PHY offline\n", chp->ch_channel);
    [all...]
siside.c 358 chp->ch_channel, drive);
370 SIS96x_REG_CBL(chp->ch_channel)) & SIS96x_REG_CBL_33) {
395 chp->ch_channel, drive, sis_tim, regtim), DEBUG_PROBE);
416 "channel %d 0x%x\n", chp->ch_channel,
417 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel))),
440 SIS_REG_CBL) & SIS_REG_CBL_33(chp->ch_channel)) {
501 "channel %d 0x%x\n", chp->ch_channel, sis_tim), DEBUG_PROBE);
502 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel),
artsata.c 160 ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200,
198 wdc_cp->ch_channel);
206 wdc_cp->ch_channel);
214 wdc_cp->ch_channel);
233 cp->ata_channel.ch_channel = channel;
  /src/sys/dev/ic/
siisata.c 248 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff);
257 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS));
258 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff);
260 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES),
278 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC),
285 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel));
303 chp->ch_channel = port;
309 "for command queue\n", chp->ch_channel);
383 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) {
386 chp->ch_channel);
    [all...]
ahcisata_core.c 410 chp->ch_channel = i;
638 AHCI_WRITE(sc, AHCI_IS, 1U << chp->ch_channel);
654 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
655 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is);
660 chp->ch_channel, is,
661 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)),
662 AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel)),
663 AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel))),
668 sact = AHCI_READ(sc, AHCI_P_CI(chp->ch_channel));
671 sact = AHCI_READ(sc, AHCI_P_SACT(chp->ch_channel));
    [all...]
wdc.c 246 device_xname(chp->ch_atac->atac_dev), chp->ch_channel,
298 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
366 chp->ch_channel, st0, st1), DEBUG_PROBE);
417 chp->ch_channel, i, error), DEBUG_PROBE);
446 chp->ch_channel, i), DEBUG_PROBE);
455 chp->ch_channel, i), DEBUG_PROBE);
467 chp->ch_channel, i), DEBUG_PROBE);
525 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
562 __func__, chp->ch_channel, st0, st1), DEBUG_PROBE);
581 __func__, chp->ch_channel, cl)
    [all...]
mvsata.c 460 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel,
631 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel, drvp->drive,
658 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel));
737 chan->chan_channel = chp->ch_channel;
781 device_xname(atac->atac_dev), chp->ch_channel, target));
850 device_xname(atac->atac_dev), chp->ch_channel, target));
895 device_xname(MVSATA_DEV2(mvport)), chp->ch_channel));
958 "channel %d: can't use EDMA\n", chp->ch_channel);
997 ", bcount=%ld\n", device_xname(atac->atac_dev), chp->ch_channel,
1029 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive))
    [all...]
wdcvar.h 137 #define CHAN_TO_WDC_REGS(chp) (&CHAN_TO_WDC(chp)->regs[(chp)->ch_channel])
  /src/sys/dev/ata/
sata_subr.c 140 device_xname(chp->ch_atac->atac_dev), chp->ch_channel);
145 device_xname(chp->ch_atac->atac_dev), chp->ch_channel);
150 device_xname(chp->ch_atac->atac_dev), chp->ch_channel,
155 device_xname(chp->ch_atac->atac_dev), chp->ch_channel,
ata_wdc.c 180 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
193 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive,
308 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive,
314 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive,
338 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
350 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive),
427 chp->ch_channel, xfer->c_drive,
462 chp->ch_channel, xfer->c_drive);
479 chp->ch_channel, xfer->c_drive);
494 chp->ch_channel, xfer->c_drive
    [all...]
  /src/sys/arch/hpcsh/dev/hd64465/
hd64465pcmcia.c 94 int ch_channel; member in struct:hd64465pcmcia_channel
300 if (ch->ch_channel == 0) {
327 ch->ch_channel = channel;
369 if (ch->ch_pcmcia && (__detect_card(ch->ch_channel) == EVENT_INSERT)) {
383 cscr = HD64461_PCCCSCR(ch->ch_channel);
398 __queue_event(ch, __detect_card(ch->ch_channel));
457 int channel = ch->ch_channel;
462 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1,
484 int channel = ch->ch_channel;
489 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1
    [all...]
  /src/sys/dev/scsipi/
atapi_wdc.c 137 chan->chan_channel = chp->ch_channel;
232 device_xname(atac->atac_dev), chp->ch_channel, drive,
248 device_xname(atac->atac_dev), chp->ch_channel, drive),
482 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel];
490 device_xname(atac->atac_dev), chp->ch_channel, drvp->drive,
540 chp->ch_channel, xfer->c_drive,
579 chp->ch_channel, xfer->c_drive,
644 chp->ch_channel, xfer->c_drive,
680 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive,
689 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive
    [all...]
  /src/sys/arch/x68k/dev/
dmacvar.h 65 int ch_channel; /* channel number */ member in struct:dmac_channel_stat
  /src/sys/arch/macppc/dev/
ki2cvar.h 93 int ch_channel; member in struct:ki2c_channel
  /src/sys/arch/hpcsh/dev/hd64461/
hd64461pcmcia.c 115 enum controller_channel ch_channel; member in struct:hd64461pcmcia_channel
368 if (ch->ch_channel == CHANNEL_0) {
395 ch->ch_channel = channel;
447 if (ch->ch_pcmcia && (detect_card(ch->ch_channel) == EVENT_INSERT)) {
472 queue_event(ch, detect_card(ch->ch_channel));
496 queue_event(ch, detect_card(ch->ch_channel));
553 int channel = ch->ch_channel;
584 int channel = ch->ch_channel;
664 hd64461pcmcia_memory_window_16(ch->ch_channel, window);
701 if (ch->ch_channel == CHANNEL_1
    [all...]
  /src/sys/arch/arm/sunxi/
sunxi_sata.c 54 const bus_size_t dma_reg = SUNXI_SATA_DMACR(chp->ch_channel);
  /src/sys/dev/podulebus/
hcide.c 99 ch->ch_channel = i;
  /src/sys/arch/arm/gemini/
obio_wdc.c 140 sc->ata_channel.ch_channel = 0;
  /src/sys/arch/evbarm/iq31244/
wdc_obio.c 111 sc->ata_channel.ch_channel = 0;

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