1 /* $NetBSD: atapi_wdc.c,v 1.141 2021/10/05 08:01:05 rin Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: atapi_wdc.c,v 1.141 2021/10/05 08:01:05 rin Exp $"); 29 30 #ifndef ATADEBUG 31 #define ATADEBUG 32 #endif /* ATADEBUG */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/file.h> 38 #include <sys/stat.h> 39 #include <sys/buf.h> 40 #include <sys/malloc.h> 41 #include <sys/device.h> 42 #include <sys/syslog.h> 43 #include <sys/proc.h> 44 #include <sys/dvdio.h> 45 46 #include <sys/intr.h> 47 #include <sys/bus.h> 48 49 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 50 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 51 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 52 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 53 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 54 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 55 56 #include <dev/ata/ataconf.h> 57 #include <dev/ata/atareg.h> 58 #include <dev/ata/atavar.h> 59 #include <dev/ic/wdcreg.h> 60 #include <dev/ic/wdcvar.h> 61 62 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 63 64 #define DEBUG_INTR 0x01 65 #define DEBUG_XFERS 0x02 66 #define DEBUG_STATUS 0x04 67 #define DEBUG_FUNCS 0x08 68 #define DEBUG_PROBE 0x10 69 #ifdef ATADEBUG 70 #ifndef ATADEBUG_ATAPI_MASK 71 #define ATADEBUG_ATAPI_MASK 0x0 72 #endif 73 int wdcdebug_atapi_mask = ATADEBUG_ATAPI_MASK; 74 #define ATADEBUG_PRINT(args, level) \ 75 if (wdcdebug_atapi_mask & (level)) \ 76 printf args 77 #else 78 #define ATADEBUG_PRINT(args, level) 79 #endif 80 81 #define ATAPI_DELAY 10 /* 10 ms, this is used only before sending a cmd */ 82 #define ATAPI_MODE_DELAY 1000 /* 1s, timeout for SET_FEATYRE cmds */ 83 84 static int wdc_atapi_get_params(struct scsipi_channel *, int, 85 struct ataparams *); 86 static void wdc_atapi_probe_device(struct atapibus_softc *, int); 87 static void wdc_atapi_minphys (struct buf *bp); 88 static int wdc_atapi_start(struct ata_channel *,struct ata_xfer *); 89 static int wdc_atapi_intr(struct ata_channel *, struct ata_xfer *, int); 90 static void wdc_atapi_kill_xfer(struct ata_channel *, 91 struct ata_xfer *, int); 92 static void wdc_atapi_phase_complete(struct ata_xfer *, int); 93 static int wdc_atapi_poll(struct ata_channel *, struct ata_xfer *); 94 static void wdc_atapi_done(struct ata_channel *, struct ata_xfer *); 95 static void wdc_atapi_reset(struct ata_channel *, struct ata_xfer *); 96 static void wdc_atapi_scsipi_request(struct scsipi_channel *, 97 scsipi_adapter_req_t, void *); 98 static void wdc_atapi_kill_pending(struct scsipi_periph *); 99 static void wdc_atapi_polldsc(void *arg); 100 101 #define MAX_SIZE MAXPHYS 102 103 static const struct scsipi_bustype wdc_atapi_bustype = { 104 .bustype_type = SCSIPI_BUSTYPE_ATAPI, 105 .bustype_cmd = atapi_scsipi_cmd, 106 .bustype_interpret_sense = atapi_interpret_sense, 107 .bustype_printaddr = atapi_print_addr, 108 .bustype_kill_pending = wdc_atapi_kill_pending, 109 .bustype_async_event_xfer_mode = NULL, 110 }; 111 112 void 113 wdc_atapibus_attach(struct atabus_softc *ata_sc) 114 { 115 struct ata_channel *chp = ata_sc->sc_chan; 116 struct atac_softc *atac = chp->ch_atac; 117 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 118 struct scsipi_channel *chan = &chp->ch_atapi_channel; 119 120 /* 121 * Fill in the scsipi_adapter. 122 */ 123 adapt->adapt_dev = atac->atac_dev; 124 adapt->adapt_nchannels = atac->atac_nchannels; 125 adapt->adapt_request = wdc_atapi_scsipi_request; 126 adapt->adapt_minphys = wdc_atapi_minphys; 127 if (atac->atac_cap & ATAC_CAP_NOIRQ) 128 adapt->adapt_flags |= SCSIPI_ADAPT_POLL_ONLY; 129 atac->atac_atapi_adapter.atapi_probe_device = wdc_atapi_probe_device; 130 131 /* 132 * Fill in the scsipi_channel. 133 */ 134 memset(chan, 0, sizeof(*chan)); 135 chan->chan_adapter = adapt; 136 chan->chan_bustype = &wdc_atapi_bustype; 137 chan->chan_channel = chp->ch_channel; 138 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 139 chan->chan_openings = 1; 140 chan->chan_max_periph = 1; 141 chan->chan_ntargets = chp->ch_ndrives; 142 chan->chan_nluns = 1; 143 144 chp->atapibus = config_found(ata_sc->sc_dev, chan, atapiprint, 145 CFARGS(.iattr = "atapi")); 146 } 147 148 static void 149 wdc_atapi_minphys(struct buf *bp) 150 { 151 152 if (bp->b_bcount > MAX_SIZE) 153 bp->b_bcount = MAX_SIZE; 154 minphys(bp); 155 } 156 157 /* 158 * Kill off all pending xfers for a periph. 159 * 160 * Must be called with adapter lock held 161 */ 162 static void 163 wdc_atapi_kill_pending(struct scsipi_periph *periph) 164 { 165 struct atac_softc *atac = 166 device_private(periph->periph_channel->chan_adapter->adapt_dev); 167 struct ata_channel *chp = 168 atac->atac_channels[periph->periph_channel->chan_channel]; 169 170 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 171 } 172 173 static void 174 wdc_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 175 { 176 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 177 bool deactivate = true; 178 179 /* remove this command from xfer queue */ 180 switch (reason) { 181 case KILL_GONE_INACTIVE: 182 deactivate = false; 183 /* FALLTHROUGH */ 184 case KILL_GONE: 185 sc_xfer->error = XS_DRIVER_STUFFUP; 186 break; 187 case KILL_RESET: 188 sc_xfer->error = XS_RESET; 189 break; 190 default: 191 printf("wdc_ata_bio_kill_xfer: unknown reason %d\n", 192 reason); 193 panic("wdc_ata_bio_kill_xfer"); 194 } 195 196 if (deactivate) 197 ata_deactivate_xfer(chp, xfer); 198 199 ata_free_xfer(chp, xfer); 200 scsipi_done(sc_xfer); 201 } 202 203 static int 204 wdc_atapi_get_params(struct scsipi_channel *chan, int drive, 205 struct ataparams *id) 206 { 207 struct wdc_softc *wdc = device_private(chan->chan_adapter->adapt_dev); 208 struct atac_softc *atac = &wdc->sc_atac; 209 struct wdc_regs *wdr = &wdc->regs[chan->chan_channel]; 210 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 211 struct ata_xfer *xfer; 212 int rv; 213 214 xfer = ata_get_xfer(chp, false); 215 if (xfer == NULL) { 216 printf("wdc_atapi_get_params: no xfer\n"); 217 return EBUSY; 218 } 219 220 xfer->c_ata_c.r_command = ATAPI_SOFT_RESET; 221 xfer->c_ata_c.r_st_bmask = 0; 222 xfer->c_ata_c.r_st_pmask = 0; 223 xfer->c_ata_c.flags = AT_WAIT | AT_POLL; 224 xfer->c_ata_c.timeout = WDC_RESET_WAIT; 225 226 wdc_exec_command(&chp->ch_drive[drive], xfer); 227 ata_wait_cmd(chp, xfer); 228 229 if (xfer->c_ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 230 ATADEBUG_PRINT(("wdc_atapi_get_params: ATAPI_SOFT_RESET " 231 "failed for drive %s:%d:%d: error 0x%x\n", 232 device_xname(atac->atac_dev), chp->ch_channel, drive, 233 xfer->c_ata_c.r_error), DEBUG_PROBE); 234 rv = -1; 235 goto out_xfer; 236 } 237 chp->ch_drive[drive].state = 0; 238 239 ata_free_xfer(chp, xfer); 240 241 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 242 243 /* Some ATAPI devices need a bit more time after software reset. */ 244 delay(5000); 245 if (ata_get_params(&chp->ch_drive[drive], AT_WAIT, id) != 0) { 246 ATADEBUG_PRINT(("wdc_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 247 "failed for drive %s:%d:%d\n", 248 device_xname(atac->atac_dev), chp->ch_channel, drive), 249 DEBUG_PROBE); 250 rv = -1; 251 goto out; 252 } 253 rv = 0; 254 out: 255 return rv; 256 257 out_xfer: 258 ata_free_xfer(chp, xfer); 259 return rv; 260 } 261 262 static void 263 wdc_atapi_probe_device(struct atapibus_softc *sc, int target) 264 { 265 struct scsipi_channel *chan = sc->sc_channel; 266 struct scsipi_periph *periph; 267 struct ataparams ids; 268 struct ataparams *id = &ids; 269 struct wdc_softc *wdc = device_private(chan->chan_adapter->adapt_dev); 270 struct atac_softc *atac = &wdc->sc_atac; 271 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 272 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 273 struct scsipibus_attach_args sa; 274 char serial_number[21], model[41], firmware_revision[9]; 275 int s; 276 277 /* skip if already attached */ 278 if (scsipi_lookup_periph(chan, target, 0) != NULL) 279 return; 280 281 /* if no ATAPI device detected at wdc attach time, skip */ 282 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 283 ATADEBUG_PRINT(("wdc_atapi_probe_device: " 284 "drive %d not present\n", target), DEBUG_PROBE); 285 return; 286 } 287 288 if (wdc_atapi_get_params(chan, target, id) == 0) { 289 #ifdef ATAPI_DEBUG_PROBE 290 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 291 device_xname(sc->sc_dev), target, 292 id->atap_config & ATAPI_CFG_CMD_MASK, 293 id->atap_config & ATAPI_CFG_DRQ_MASK); 294 #endif 295 periph = scsipi_alloc_periph(M_WAITOK); 296 periph->periph_dev = NULL; 297 periph->periph_channel = chan; 298 periph->periph_switch = &atapi_probe_periphsw; 299 periph->periph_target = target; 300 periph->periph_lun = 0; 301 periph->periph_quirks = PQUIRK_ONLYBIG; 302 303 #ifdef SCSIPI_DEBUG 304 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 305 SCSIPI_DEBUG_TARGET == target) 306 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 307 #endif 308 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 309 if (id->atap_config & ATAPI_CFG_REMOV) 310 periph->periph_flags |= PERIPH_REMOVABLE; 311 if (periph->periph_type == T_SEQUENTIAL) { 312 s = splbio(); 313 drvp->drive_flags |= ATA_DRIVE_ATAPIDSCW; 314 splx(s); 315 } 316 317 sa.sa_periph = periph; 318 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 319 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 320 T_REMOV : T_FIXED; 321 strnvisx(model, sizeof(model), id->atap_model, 322 sizeof(id->atap_model), VIS_TRIM|VIS_SAFE|VIS_OCTAL); 323 strnvisx(serial_number, sizeof(serial_number), 324 id->atap_serial, sizeof(id->atap_serial), 325 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 326 strnvisx(firmware_revision, sizeof(firmware_revision), 327 id->atap_revision, sizeof(id->atap_revision), 328 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 329 sa.sa_inqbuf.vendor = model; 330 sa.sa_inqbuf.product = serial_number; 331 sa.sa_inqbuf.revision = firmware_revision; 332 333 /* 334 * Determine the operating mode capabilities of the device. 335 */ 336 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 337 periph->periph_cap |= PERIPH_CAP_CMD16; 338 /* XXX This is gross. */ 339 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 340 341 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 342 343 if (drvp->drv_softc) 344 ata_probe_caps(drvp); 345 else { 346 s = splbio(); 347 drvp->drive_type = ATA_DRIVET_NONE; 348 splx(s); 349 } 350 } else { 351 s = splbio(); 352 drvp->drive_type = ATA_DRIVET_NONE; 353 splx(s); 354 } 355 } 356 357 static const struct ata_xfer_ops wdc_atapi_xfer_ops = { 358 .c_start = wdc_atapi_start, 359 .c_intr = wdc_atapi_intr, 360 .c_poll = wdc_atapi_poll, 361 .c_abort = wdc_atapi_reset, 362 .c_kill_xfer = wdc_atapi_kill_xfer, 363 }; 364 365 static void 366 wdc_atapi_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 367 void *arg) 368 { 369 struct scsipi_adapter *adapt = chan->chan_adapter; 370 struct scsipi_periph *periph; 371 struct scsipi_xfer *sc_xfer; 372 struct wdc_softc *wdc = device_private(adapt->adapt_dev); 373 struct atac_softc *atac = &wdc->sc_atac; 374 struct ata_xfer *xfer; 375 int channel = chan->chan_channel; 376 int drive, s; 377 378 switch (req) { 379 case ADAPTER_REQ_RUN_XFER: 380 sc_xfer = arg; 381 periph = sc_xfer->xs_periph; 382 drive = periph->periph_target; 383 384 ATADEBUG_PRINT(("wdc_atapi_scsipi_request %s:%d:%d\n", 385 device_xname(atac->atac_dev), channel, drive), 386 DEBUG_XFERS); 387 if (!device_is_active(atac->atac_dev)) { 388 sc_xfer->error = XS_DRIVER_STUFFUP; 389 scsipi_done(sc_xfer); 390 return; 391 } 392 393 xfer = ata_get_xfer(atac->atac_channels[channel], false); 394 if (xfer == NULL) { 395 sc_xfer->error = XS_RESOURCE_SHORTAGE; 396 scsipi_done(sc_xfer); 397 return; 398 } 399 400 if (sc_xfer->xs_control & XS_CTL_POLL) 401 xfer->c_flags |= C_POLL; 402 #if NATA_DMA 403 if ((atac->atac_channels[channel]->ch_drive[drive].drive_flags & 404 (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && sc_xfer->datalen > 0) 405 xfer->c_flags |= C_DMA; 406 #endif 407 #if NATA_DMA && NATA_PIOBM 408 else 409 #endif 410 #if NATA_PIOBM 411 if ((atac->atac_cap & ATAC_CAP_PIOBM) && 412 sc_xfer->datalen > 0) 413 xfer->c_flags |= C_PIOBM; 414 #endif 415 xfer->c_drive = drive; 416 xfer->c_flags |= C_ATAPI; 417 #if NATA_DMA 418 if (sc_xfer->cmd->opcode == GPCMD_REPORT_KEY || 419 sc_xfer->cmd->opcode == GPCMD_SEND_KEY || 420 sc_xfer->cmd->opcode == GPCMD_READ_DVD_STRUCTURE) { 421 /* 422 * DVD authentication commands must always be done in 423 * PIO mode. 424 */ 425 xfer->c_flags &= ~C_DMA; 426 } 427 428 /* 429 * DMA normally can't deal with transfers which are not a 430 * multiple of its databus width. It's a bug to request odd 431 * length transfers for ATAPI. 432 * 433 * Some devices also can't cope with unaligned DMA xfers 434 * either. Also some devices seem to not handle DMA xfers of 435 * less than 4 bytes. 436 * 437 * By enforcing at least 4 byte aligned offset and length for 438 * DMA, we might use PIO where DMA could be allowed but better 439 * safe than sorry as recent problems proved. 440 * 441 * Offending structures that are thus done by PIO instead of 442 * DMA are normally small structures since all bulkdata is 443 * aligned. But as the request may come from userland, we have 444 * to protect against it anyway. 445 * 446 * XXX check for the 32 bit wide flag? 447 */ 448 449 if (((uintptr_t) sc_xfer->data) & 0x03) 450 xfer->c_flags &= ~C_DMA; 451 if ((sc_xfer->datalen < 4) || (sc_xfer->datalen & 0x03)) 452 xfer->c_flags &= ~C_DMA; 453 #endif /* NATA_DMA */ 454 455 xfer->c_databuf = sc_xfer->data; 456 xfer->c_bcount = sc_xfer->datalen; 457 xfer->ops = &wdc_atapi_xfer_ops; 458 xfer->c_scsipi = sc_xfer; 459 xfer->c_atapi.c_dscpoll = 0; 460 s = splbio(); 461 ata_exec_xfer(atac->atac_channels[channel], xfer); 462 #ifdef DIAGNOSTIC 463 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 464 (sc_xfer->xs_status & XS_STS_DONE) == 0) 465 panic("wdc_atapi_scsipi_request: polled command " 466 "not done"); 467 #endif 468 splx(s); 469 return; 470 471 default: 472 /* Not supported, nothing to do. */ 473 ; 474 } 475 } 476 477 static int 478 wdc_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 479 { 480 struct atac_softc *atac = chp->ch_atac; 481 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 482 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 483 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 484 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 485 int wait_flags = (sc_xfer->xs_control & XS_CTL_POLL) ? AT_POLL : 0; 486 int tfd; 487 const char *errstring; 488 489 ATADEBUG_PRINT(("wdc_atapi_start %s:%d:%d, scsi flags 0x%x \n", 490 device_xname(atac->atac_dev), chp->ch_channel, drvp->drive, 491 sc_xfer->xs_control), DEBUG_XFERS); 492 493 ata_channel_lock_owned(chp); 494 495 #if NATA_DMA 496 if ((xfer->c_flags & C_DMA) && (drvp->n_xfers <= NXFER)) 497 drvp->n_xfers++; 498 #endif 499 /* Do control operations specially. */ 500 if (__predict_false(drvp->state < READY)) { 501 /* If it's not a polled command, we need the kernel thread */ 502 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0 503 && !ata_is_thread_run(chp)) 504 return ATASTART_TH; 505 /* 506 * disable interrupts, all commands here should be quick 507 * enough to be able to poll, and we don't go here that often 508 */ 509 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 510 WDCTL_4BIT | WDCTL_IDS); 511 if (wdc->select) 512 wdc->select(chp, xfer->c_drive); 513 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 514 WDSD_IBM | (xfer->c_drive << 4)); 515 /* Don't try to set mode if controller can't be adjusted */ 516 if (atac->atac_set_modes == NULL) 517 goto ready; 518 /* Also don't try if the drive didn't report its mode */ 519 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 520 goto ready; 521 errstring = "unbusy"; 522 if (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd)) 523 goto timeout; 524 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 525 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 526 errstring = "piomode"; 527 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 528 &tfd)) 529 goto timeout; 530 if (ATACH_ST(tfd) & WDCS_ERR) { 531 if (ATACH_ST(tfd) == WDCE_ABRT) { 532 /* 533 * Some ATAPI drives reject PIO settings. 534 * Fall back to PIO mode 3 since that's the 535 * minimum for ATAPI. 536 */ 537 printf("%s:%d:%d: PIO mode %d rejected, " 538 "falling back to PIO mode 3\n", 539 device_xname(atac->atac_dev), 540 chp->ch_channel, xfer->c_drive, 541 drvp->PIO_mode); 542 if (drvp->PIO_mode > 3) 543 drvp->PIO_mode = 3; 544 } else 545 goto error; 546 } 547 #if NATA_DMA 548 #if NATA_UDMA 549 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 550 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 551 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 552 } else 553 #endif 554 if (drvp->drive_flags & ATA_DRIVE_DMA) { 555 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 556 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 557 } else { 558 goto ready; 559 } 560 errstring = "dmamode"; 561 if (wdc_wait_for_unbusy(chp, ATAPI_MODE_DELAY, wait_flags, 562 &tfd)) 563 goto timeout; 564 if (ATACH_ST(tfd) & WDCS_ERR) { 565 if (ATACH_ERR(tfd) == WDCE_ABRT) { 566 #if NATA_UDMA 567 if (drvp->drive_flags & ATA_DRIVE_UDMA) 568 goto error; 569 else 570 #endif 571 { 572 /* 573 * The drive rejected our DMA setting. 574 * Fall back to mode 1. 575 */ 576 printf("%s:%d:%d: DMA mode %d rejected, " 577 "falling back to DMA mode 0\n", 578 device_xname(atac->atac_dev), 579 chp->ch_channel, xfer->c_drive, 580 drvp->DMA_mode); 581 if (drvp->DMA_mode > 0) 582 drvp->DMA_mode = 0; 583 } 584 } else 585 goto error; 586 } 587 #endif /* NATA_DMA */ 588 ready: 589 drvp->state = READY; 590 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 591 WDCTL_4BIT); 592 delay(10); /* some drives need a little delay here */ 593 } 594 /* start timeout machinery */ 595 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) 596 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 597 wdctimeout, chp); 598 599 if (wdc->select) 600 wdc->select(chp, xfer->c_drive); 601 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 602 WDSD_IBM | (xfer->c_drive << 4)); 603 switch (wdc_wait_for_unbusy(chp, ATAPI_DELAY, wait_flags, &tfd)) { 604 case WDCWAIT_OK: 605 break; 606 case WDCWAIT_TOUT: 607 printf("wdc_atapi_start: not ready, st = %02x\n", 608 ATACH_ST(tfd)); 609 sc_xfer->error = XS_TIMEOUT; 610 return ATASTART_ABORT; 611 case WDCWAIT_THR: 612 return ATASTART_TH; 613 } 614 615 /* 616 * Even with WDCS_ERR, the device should accept a command packet 617 * Limit length to what can be stuffed into the cylinder register 618 * (16 bits). Some CD-ROMs seem to interpret '0' as 65536, 619 * but not all devices do that and it's not obvious from the 620 * ATAPI spec that that behaviour should be expected. If more 621 * data is necessary, multiple data transfer phases will be done. 622 */ 623 624 wdccommand(chp, xfer->c_drive, ATAPI_PKT_CMD, 625 xfer->c_bcount <= 0xffff ? xfer->c_bcount : 0xffff, 626 0, 0, 0, 627 #if NATA_DMA 628 (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 629 #endif 630 0 631 ); 632 633 #if NATA_PIOBM 634 if (xfer->c_flags & C_PIOBM) { 635 int error; 636 int dma_flags = (sc_xfer->xs_control & XS_CTL_DATA_IN) 637 ? WDC_DMA_READ : 0; 638 if (xfer->c_flags & C_POLL) { 639 /* XXX not supported yet --- fall back to PIO */ 640 xfer->c_flags &= ~C_PIOBM; 641 } else { 642 /* Init the DMA channel. */ 643 error = (*wdc->dma_init)(wdc->dma_arg, 644 chp->ch_channel, xfer->c_drive, 645 (char *)xfer->c_databuf, 646 xfer->c_bcount, 647 dma_flags | WDC_DMA_PIOBM_ATAPI); 648 if (error) { 649 if (error == EINVAL) { 650 /* 651 * We can't do DMA on this transfer 652 * for some reason. Fall back to 653 * PIO. 654 */ 655 xfer->c_flags &= ~C_PIOBM; 656 error = 0; 657 } else { 658 sc_xfer->error = XS_DRIVER_STUFFUP; 659 errstring = "piobm"; 660 goto error; 661 } 662 } 663 } 664 } 665 #endif 666 /* 667 * If there is no interrupt for CMD input, busy-wait for it (done in 668 * the interrupt routine. Poll routine will exit early in this case. 669 */ 670 if ((sc_xfer->xs_periph->periph_cap & ATAPI_CFG_DRQ_MASK) != 671 ATAPI_CFG_IRQ_DRQ || (sc_xfer->xs_control & XS_CTL_POLL)) 672 return ATASTART_POLL; 673 else { 674 chp->ch_flags |= ATACH_IRQ_WAIT; 675 return ATASTART_STARTED; 676 } 677 678 timeout: 679 printf("%s:%d:%d: %s timed out\n", 680 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 681 errstring); 682 sc_xfer->error = XS_TIMEOUT; 683 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 684 delay(10); /* some drives need a little delay here */ 685 return ATASTART_ABORT; 686 687 error: 688 printf("%s:%d:%d: %s ", 689 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 690 errstring); 691 printf("error (0x%x)\n", ATACH_ERR(tfd)); 692 sc_xfer->error = XS_SHORTSENSE; 693 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 694 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 695 delay(10); /* some drives need a little delay here */ 696 return ATASTART_ABORT; 697 } 698 699 static int 700 wdc_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 701 { 702 /* 703 * If there is no interrupt for CMD input, busy-wait for it (done in 704 * the interrupt routine. If it is a polled command, call the interrupt 705 * routine until command is done. 706 */ 707 const bool poll = ((xfer->c_scsipi->xs_control & XS_CTL_POLL) != 0); 708 709 /* Wait for at last 400ns for status bit to be valid */ 710 DELAY(1); 711 wdc_atapi_intr(chp, xfer, 0); 712 713 if (!poll) 714 return ATAPOLL_DONE; 715 716 #if NATA_DMA 717 if (chp->ch_flags & ATACH_DMA_WAIT) { 718 wdc_dmawait(chp, xfer, xfer->c_scsipi->timeout); 719 chp->ch_flags &= ~ATACH_DMA_WAIT; 720 } 721 #endif 722 while ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 723 /* Wait for at last 400ns for status bit to be valid */ 724 DELAY(1); 725 wdc_atapi_intr(chp, xfer, 0); 726 } 727 728 return ATAPOLL_DONE; 729 } 730 731 static int 732 wdc_atapi_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 733 { 734 struct atac_softc *atac = chp->ch_atac; 735 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 736 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 737 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 738 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 739 int len, phase, i, retries=0; 740 int ire, tfd; 741 #if NATA_DMA 742 int error; 743 #endif 744 #if NATA_DMA || NATA_PIOBM 745 int dma_flags = 0; 746 #endif 747 void *cmd; 748 749 ATADEBUG_PRINT(("wdc_atapi_intr %s:%d:%d\n", 750 device_xname(atac->atac_dev), chp->ch_channel, drvp->drive), 751 DEBUG_INTR); 752 753 ata_channel_lock(chp); 754 755 /* Is it not a transfer, but a control operation? */ 756 if (drvp->state < READY) { 757 printf("%s:%d:%d: bad state %d in wdc_atapi_intr\n", 758 device_xname(atac->atac_dev), chp->ch_channel, 759 xfer->c_drive, drvp->state); 760 panic("wdc_atapi_intr: bad state"); 761 } 762 /* 763 * If we missed an interrupt in a PIO transfer, reset and restart. 764 * Don't try to continue transfer, we may have missed cycles. 765 */ 766 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 767 ata_channel_unlock(chp); 768 sc_xfer->error = XS_TIMEOUT; 769 wdc_atapi_reset(chp, xfer); 770 return 1; 771 } 772 773 #if NATA_PIOBM 774 /* Transfer-done interrupt for busmastering PIO operation */ 775 if ((xfer->c_flags & C_PIOBM) && (chp->ch_flags & ATACH_PIOBM_WAIT)) { 776 chp->ch_flags &= ~ATACH_PIOBM_WAIT; 777 778 /* restore transfer length */ 779 len = xfer->c_bcount; 780 if (xfer->c_atapi.c_lenoff < 0) 781 len += xfer->c_atapi.c_lenoff; 782 783 if (sc_xfer->xs_control & XS_CTL_DATA_IN) 784 goto end_piobm_datain; 785 else 786 goto end_piobm_dataout; 787 } 788 #endif 789 790 /* Ack interrupt done in wdc_wait_for_unbusy */ 791 if (wdc->select) 792 wdc->select(chp, xfer->c_drive); 793 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 794 WDSD_IBM | (xfer->c_drive << 4)); 795 if (wdc_wait_for_unbusy(chp, 796 (irq == 0) ? sc_xfer->timeout : 0, AT_POLL, &tfd) == WDCWAIT_TOUT) { 797 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 798 ata_channel_unlock(chp); 799 return 0; /* IRQ was not for us */ 800 } 801 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip=%d\n", 802 device_xname(atac->atac_dev), chp->ch_channel, 803 xfer->c_drive, xfer->c_bcount, xfer->c_skip); 804 #if NATA_DMA 805 if (xfer->c_flags & C_DMA) { 806 ata_dmaerr(drvp, 807 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 808 } 809 #endif 810 sc_xfer->error = XS_TIMEOUT; 811 ata_channel_unlock(chp); 812 wdc_atapi_reset(chp, xfer); 813 return 1; 814 } 815 if (wdc->irqack) 816 wdc->irqack(chp); 817 818 #if NATA_DMA 819 /* 820 * If we missed an IRQ and were using DMA, flag it as a DMA error 821 * and reset device. 822 */ 823 if ((xfer->c_flags & C_TIMEOU) && (xfer->c_flags & C_DMA)) { 824 ata_dmaerr(drvp, (xfer->c_flags & C_POLL) ? AT_POLL : 0); 825 sc_xfer->error = XS_RESET; 826 ata_channel_unlock(chp); 827 wdc_atapi_reset(chp, xfer); 828 return (1); 829 } 830 #endif 831 /* 832 * if the request sense command was aborted, report the short sense 833 * previously recorded, else continue normal processing 834 */ 835 836 #if NATA_DMA || NATA_PIOBM 837 if (xfer->c_flags & (C_DMA | C_PIOBM)) 838 dma_flags = (sc_xfer->xs_control & XS_CTL_DATA_IN) 839 ? WDC_DMA_READ : 0; 840 #endif 841 again: 842 len = bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0) + 843 256 * bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 0); 844 ire = bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_ireason], 0); 845 phase = (ire & (WDCI_CMD | WDCI_IN)) | (ATACH_ST(tfd) & WDCS_DRQ); 846 ATADEBUG_PRINT(("wdc_atapi_intr: c_bcount %d len %d st 0x%x err 0x%x " 847 "ire 0x%x :", xfer->c_bcount, 848 len, ATACH_ST(tfd), ATACH_ERR(tfd), ire), DEBUG_INTR); 849 850 switch (phase) { 851 case PHASE_CMDOUT: 852 cmd = sc_xfer->cmd; 853 ATADEBUG_PRINT(("PHASE_CMDOUT\n"), DEBUG_INTR); 854 #if NATA_DMA 855 /* Init the DMA channel if necessary */ 856 if (xfer->c_flags & C_DMA) { 857 error = (*wdc->dma_init)(wdc->dma_arg, 858 chp->ch_channel, xfer->c_drive, 859 xfer->c_databuf, xfer->c_bcount, dma_flags); 860 if (error) { 861 if (error == EINVAL) { 862 /* 863 * We can't do DMA on this transfer 864 * for some reason. Fall back to 865 * PIO. 866 */ 867 xfer->c_flags &= ~C_DMA; 868 error = 0; 869 } else { 870 sc_xfer->error = XS_DRIVER_STUFFUP; 871 break; 872 } 873 } 874 } 875 #endif 876 877 /* send packet command */ 878 /* Commands are 12 or 16 bytes long. It's 32-bit aligned */ 879 wdc->dataout_pio(chp, drvp->drive_flags, cmd, sc_xfer->cmdlen); 880 881 #if NATA_DMA 882 /* Start the DMA channel if necessary */ 883 if (xfer->c_flags & C_DMA) { 884 (*wdc->dma_start)(wdc->dma_arg, 885 chp->ch_channel, xfer->c_drive); 886 chp->ch_flags |= ATACH_DMA_WAIT; 887 } 888 #endif 889 890 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) { 891 chp->ch_flags |= ATACH_IRQ_WAIT; 892 } 893 894 ata_channel_unlock(chp); 895 return 1; 896 897 case PHASE_DATAOUT: 898 /* write data */ 899 ATADEBUG_PRINT(("PHASE_DATAOUT\n"), DEBUG_INTR); 900 #if NATA_DMA 901 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT) == 0 || 902 (xfer->c_flags & C_DMA) != 0) { 903 printf("wdc_atapi_intr: bad data phase DATAOUT\n"); 904 if (xfer->c_flags & C_DMA) { 905 ata_dmaerr(drvp, 906 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 907 } 908 sc_xfer->error = XS_TIMEOUT; 909 ata_channel_unlock(chp); 910 wdc_atapi_reset(chp, xfer); 911 return 1; 912 } 913 #endif 914 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 915 if (xfer->c_bcount < len) { 916 printf("wdc_atapi_intr: warning: write only " 917 "%d of %d requested bytes\n", xfer->c_bcount, len); 918 len = xfer->c_bcount; 919 } 920 921 #if NATA_PIOBM 922 if (xfer->c_flags & C_PIOBM) { 923 /* start the busmastering PIO */ 924 (*wdc->piobm_start)(wdc->dma_arg, 925 chp->ch_channel, xfer->c_drive, 926 xfer->c_skip, len, WDC_PIOBM_XFER_IRQ); 927 chp->ch_flags |= ATACH_DMA_WAIT | ATACH_IRQ_WAIT | 928 ATACH_PIOBM_WAIT; 929 ata_channel_unlock(chp); 930 return 1; 931 } 932 #endif 933 wdc->dataout_pio(chp, drvp->drive_flags, 934 (char *)xfer->c_databuf + xfer->c_skip, len); 935 936 #if NATA_PIOBM 937 end_piobm_dataout: 938 #endif 939 for (i = xfer->c_atapi.c_lenoff; i > 0; i -= 2) 940 bus_space_write_2(wdr->cmd_iot, 941 wdr->cmd_iohs[wd_data], 0, 0); 942 943 xfer->c_skip += len; 944 xfer->c_bcount -= len; 945 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) { 946 chp->ch_flags |= ATACH_IRQ_WAIT; 947 } 948 ata_channel_unlock(chp); 949 return 1; 950 951 case PHASE_DATAIN: 952 /* Read data */ 953 ATADEBUG_PRINT(("PHASE_DATAIN\n"), DEBUG_INTR); 954 #if NATA_DMA 955 if ((sc_xfer->xs_control & XS_CTL_DATA_IN) == 0 || 956 (xfer->c_flags & C_DMA) != 0) { 957 printf("wdc_atapi_intr: bad data phase DATAIN\n"); 958 if (xfer->c_flags & C_DMA) { 959 ata_dmaerr(drvp, 960 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 961 } 962 sc_xfer->error = XS_TIMEOUT; 963 ata_channel_unlock(chp); 964 wdc_atapi_reset(chp, xfer); 965 return 1; 966 } 967 #endif 968 xfer->c_atapi.c_lenoff = len - xfer->c_bcount; 969 if (xfer->c_bcount < len) { 970 printf("wdc_atapi_intr: warning: reading only " 971 "%d of %d bytes\n", xfer->c_bcount, len); 972 len = xfer->c_bcount; 973 } 974 975 #if NATA_PIOBM 976 if (xfer->c_flags & C_PIOBM) { 977 /* start the busmastering PIO */ 978 (*wdc->piobm_start)(wdc->dma_arg, 979 chp->ch_channel, xfer->c_drive, 980 xfer->c_skip, len, WDC_PIOBM_XFER_IRQ); 981 chp->ch_flags |= ATACH_DMA_WAIT | ATACH_IRQ_WAIT | 982 ATACH_PIOBM_WAIT; 983 ata_channel_unlock(chp); 984 return 1; 985 } 986 #endif 987 wdc->datain_pio(chp, drvp->drive_flags, 988 (char *)xfer->c_databuf + xfer->c_skip, len); 989 990 #if NATA_PIOBM 991 end_piobm_datain: 992 #endif 993 if (xfer->c_atapi.c_lenoff > 0) 994 wdcbit_bucket(chp, xfer->c_atapi.c_lenoff); 995 996 xfer->c_skip += len; 997 xfer->c_bcount -= len; 998 if ((sc_xfer->xs_control & XS_CTL_POLL) == 0) { 999 chp->ch_flags |= ATACH_IRQ_WAIT; 1000 } 1001 ata_channel_unlock(chp); 1002 return 1; 1003 1004 case PHASE_ABORTED: 1005 case PHASE_COMPLETED: 1006 ATADEBUG_PRINT(("PHASE_COMPLETED\n"), DEBUG_INTR); 1007 #if NATA_DMA 1008 if (xfer->c_flags & C_DMA) { 1009 xfer->c_bcount -= sc_xfer->datalen; 1010 } 1011 #endif 1012 sc_xfer->resid = xfer->c_bcount; 1013 /* this will unlock channel lock too */ 1014 wdc_atapi_phase_complete(xfer, tfd); 1015 return(1); 1016 1017 default: 1018 if (++retries<500) { 1019 DELAY(100); 1020 tfd = ATACH_ERR_ST( 1021 bus_space_read_1(wdr->cmd_iot, 1022 wdr->cmd_iohs[wd_error], 0), 1023 bus_space_read_1(wdr->cmd_iot, 1024 wdr->cmd_iohs[wd_status], 0) 1025 ); 1026 goto again; 1027 } 1028 printf("wdc_atapi_intr: unknown phase 0x%x\n", phase); 1029 if (ATACH_ST(tfd) & WDCS_ERR) { 1030 sc_xfer->error = XS_SHORTSENSE; 1031 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 1032 } else { 1033 #if NATA_DMA 1034 if (xfer->c_flags & C_DMA) { 1035 ata_dmaerr(drvp, 1036 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1037 } 1038 #endif 1039 sc_xfer->error = XS_RESET; 1040 ata_channel_unlock(chp); 1041 wdc_atapi_reset(chp, xfer); 1042 return (1); 1043 } 1044 } 1045 ATADEBUG_PRINT(("wdc_atapi_intr: wdc_atapi_done() (end), error 0x%x " 1046 "sense 0x%x\n", sc_xfer->error, sc_xfer->sense.atapi_sense), 1047 DEBUG_INTR); 1048 ata_channel_unlock(chp); 1049 wdc_atapi_done(chp, xfer); 1050 return (1); 1051 } 1052 1053 static void 1054 wdc_atapi_phase_complete(struct ata_xfer *xfer, int tfd) 1055 { 1056 struct ata_channel *chp = xfer->c_chp; 1057 struct atac_softc *atac = chp->ch_atac; 1058 #if NATA_DMA || NATA_PIOBM 1059 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1060 #endif 1061 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1062 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1063 1064 ata_channel_lock_owned(chp); 1065 1066 /* wait for DSC if needed */ 1067 if (drvp->drive_flags & ATA_DRIVE_ATAPIDSCW) { 1068 ATADEBUG_PRINT(("wdc_atapi_phase_complete(%s:%d:%d) " 1069 "polldsc %d\n", device_xname(atac->atac_dev), 1070 chp->ch_channel, 1071 xfer->c_drive, xfer->c_atapi.c_dscpoll), DEBUG_XFERS); 1072 #if 1 1073 if (cold) 1074 panic("wdc_atapi_phase_complete: cold"); 1075 #endif 1076 if (wdcwait(chp, WDCS_DSC, WDCS_DSC, 10, 1077 AT_POLL, &tfd) == WDCWAIT_TOUT) { 1078 /* 10ms not enough, try again in 1 tick */ 1079 if (xfer->c_atapi.c_dscpoll++ > 1080 mstohz(sc_xfer->timeout)) { 1081 printf("%s:%d:%d: wait_for_dsc " 1082 "failed\n", 1083 device_xname(atac->atac_dev), 1084 chp->ch_channel, xfer->c_drive); 1085 ata_channel_unlock(chp); 1086 sc_xfer->error = XS_TIMEOUT; 1087 wdc_atapi_reset(chp, xfer); 1088 } else { 1089 callout_reset(&chp->c_timo_callout, 1, 1090 wdc_atapi_polldsc, chp); 1091 ata_channel_unlock(chp); 1092 } 1093 return; 1094 } 1095 } 1096 1097 /* 1098 * Some drive occasionally set WDCS_ERR with 1099 * "ATA illegal length indication" in the error 1100 * register. If we read some data the sense is valid 1101 * anyway, so don't report the error. 1102 */ 1103 if (ATACH_ST(tfd) & WDCS_ERR && 1104 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1105 sc_xfer->resid == sc_xfer->datalen)) { 1106 /* save the short sense */ 1107 sc_xfer->error = XS_SHORTSENSE; 1108 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 1109 if ((sc_xfer->xs_periph->periph_quirks & 1110 PQUIRK_NOSENSE) == 0) { 1111 /* ask scsipi to send a REQUEST_SENSE */ 1112 sc_xfer->error = XS_BUSY; 1113 sc_xfer->status = SCSI_CHECK; 1114 } 1115 #if NATA_DMA || NATA_PIOBM 1116 else if (wdc->dma_status & 1117 (WDC_DMAST_NOIRQ | WDC_DMAST_ERR)) { 1118 #if NATA_DMA 1119 ata_dmaerr(drvp, 1120 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 1121 #endif 1122 sc_xfer->error = XS_RESET; 1123 ata_channel_unlock(chp); 1124 wdc_atapi_reset(chp, xfer); 1125 return; 1126 } 1127 #endif 1128 } 1129 if (xfer->c_bcount != 0) { 1130 ATADEBUG_PRINT(("wdc_atapi_intr: bcount value is " 1131 "%d after io\n", xfer->c_bcount), DEBUG_XFERS); 1132 } 1133 #ifdef DIAGNOSTIC 1134 if (xfer->c_bcount < 0) { 1135 printf("wdc_atapi_intr warning: bcount value " 1136 "is %d after io\n", xfer->c_bcount); 1137 } 1138 #endif 1139 ATADEBUG_PRINT(("wdc_atapi_phase_complete: wdc_atapi_done(), " 1140 "error 0x%x sense 0x%x\n", sc_xfer->error, 1141 sc_xfer->sense.atapi_sense), DEBUG_INTR); 1142 ata_channel_unlock(chp); 1143 wdc_atapi_done(chp, xfer); 1144 } 1145 1146 static void 1147 wdc_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer) 1148 { 1149 struct atac_softc *atac = chp->ch_atac; 1150 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1151 1152 ATADEBUG_PRINT(("wdc_atapi_done %s:%d:%d: flags 0x%x\n", 1153 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1154 (u_int)xfer->c_flags), DEBUG_XFERS); 1155 1156 if (ata_waitdrain_xfer_check(chp, xfer)) 1157 return; 1158 1159 ata_deactivate_xfer(chp, xfer); 1160 ata_free_xfer(chp, xfer); 1161 1162 ATADEBUG_PRINT(("wdc_atapi_done: scsipi_done\n"), DEBUG_XFERS); 1163 scsipi_done(sc_xfer); 1164 ATADEBUG_PRINT(("atastart from wdc_atapi_done, flags 0x%x\n", 1165 chp->ch_flags), DEBUG_XFERS); 1166 atastart(chp); 1167 } 1168 1169 static void 1170 wdc_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 1171 { 1172 struct atac_softc *atac = chp->ch_atac; 1173 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1174 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1175 int tfd; 1176 1177 ata_channel_lock(chp); 1178 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 1179 drvp->state = 0; 1180 if (wdc_wait_for_unbusy(chp, WDC_RESET_WAIT, AT_POLL, &tfd) != 0) { 1181 printf("%s:%d:%d: reset failed\n", 1182 device_xname(atac->atac_dev), chp->ch_channel, 1183 xfer->c_drive); 1184 sc_xfer->error = XS_SELTIMEOUT; 1185 } 1186 ata_channel_unlock(chp); 1187 wdc_atapi_done(chp, xfer); 1188 return; 1189 } 1190 1191 static void 1192 wdc_atapi_polldsc(void *arg) 1193 { 1194 struct ata_channel *chp = arg; 1195 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 1196 1197 KASSERT(xfer != NULL); 1198 1199 ata_channel_lock(chp); 1200 1201 /* this will unlock channel lock too */ 1202 wdc_atapi_phase_complete(xfer, 0); 1203 } 1204
Indexes created Sun Sep 21 15:09:59 GMT 2025