| /src/sys/dev/clk/ |
| clk.h | 38 int clk_set_rate(struct clk *, u_int);
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| clk.c | 230 clk_set_rate(struct clk *clk, u_int rate) function in typeref:typename:int
235 return clk_set_rate(clk_get_parent(clk), rate);
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| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu_display.c | 63 error = clk_set_rate(clkp, new_rate / 2);
68 error = clk_set_rate(clkp, new_rate);
135 error = clk_set_rate(pllclkp, best_parent_rate);
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| sunxi_ccu_fixed_factor.c | 76 return clk_set_rate(clkp_parent, rate);
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| sunxi_gmac.c | 176 if (clk_set_rate(clk_gmac_tx, GMAC_TX_RATE_MII) != 0) {
181 if (clk_set_rate(clk_gmac_tx, GMAC_TX_RATE_RGMII) != 0) {
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| sun50i_a64_ccu.c | 645 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_DE].base, 420000000);
648 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_VIDEO0].base, 297000000);
649 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_VIDEO1].base, 297000000);
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| sun4i_a10_ccu.c | 753 error = clk_set_rate(clkp, rate);
755 error = clk_set_rate(clkp, rate / 2);
835 error = clk_set_rate(pllclk, 3000000 * n);
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| /src/sys/arch/arm/amlogic/ |
| meson_clk_fixed_factor.c | 76 return clk_set_rate(clkp_parent, rate);
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| meson_clk_div.c | 97 return clk_set_rate(clkp_parent, new_rate);
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| meson_clk_pll.c | 116 return clk_set_rate(clkp_parent, new_rate);
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| /src/sys/arch/arm/nxp/ |
| imx_ccm_extclk.c | 80 return clk_set_rate(extclk, rate);
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| imx_ccm_fixed_factor.c | 76 return clk_set_rate(clkp_parent, rate);
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| imx_ccm_div.c | 83 return clk_set_rate(clkp, rate);
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| imx_ccm.c | 117 return clk_set_rate(clkp_parent, rate);
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| imx_ccm_composite.c | 107 return clk_set_rate(clk_parent, rate);
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| /src/sys/arch/riscv/starfive/ |
| jh7100_gmac.c | 83 int error = clk_set_rate(jheth_sc->sc_clk_tx, rate);
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| /src/sys/arch/arm/nvidia/ |
| tegra_hdaudio.c | 200 error = clk_set_rate(sc->sc_clk_hda, 48000000);
222 error = clk_set_rate(sc->sc_clk_hda2codec_2x, 48000000);
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| tegra_sdhc.c | 202 error = clk_set_rate(sc->sc_clk, 100000000);
204 error = clk_set_rate(sc->sc_clk, 204000000);
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| tegra_ahcisata.c | 373 error = clk_set_rate(sc->sc_clk_sata_oob, 204000000);
381 error = clk_set_rate(sc->sc_clk_sata, 102000000);
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| tegra_xusb.c | 321 error = clk_set_rate(clk, 102000000);
332 error = clk_set_rate(clk, 204000000);
358 error = clk_set_rate(psc->sc_clk_ss_src, 2000000);
367 error = clk_set_rate(psc->sc_clk_ss_src, 120000000);
558 error = clk_set_rate(psc->sc_clk_ss_src, data * 1000);
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| tegra_soctherm.c | 237 error = clk_set_rate(sc->sc_clk_soctherm, 51000000);
244 error = clk_set_rate(sc->sc_clk_tsensor, 400000);
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| tegra124_cpu.c | 277 error = clk_set_rate(tegra124_clk_pllx, r->rate * 1000000);
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| /src/sys/arch/arm/rockchip/ |
| rk_cru_arm.c | 98 error = clk_set_rate(&main_parent->base, parent_rate);
153 error = clk_set_rate(&main_parent->base, rate);
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| rk_cru_composite.c | 153 return clk_set_rate(clk_parent, rate);
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| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/device/ |
| nouveau_nvkm_engine_device_tegra.c | 57 clk_set_rate(tdev->clk_pwr, 204000000);
329 ret = clk_set_rate(tdev->clk, ULONG_MAX);
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