1 /* $NetBSD: tegra_soctherm.c,v 1.13 2021/01/27 03:10:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_soctherm.c,v 1.13 2021/01/27 03:10:19 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 40 #include <dev/sysmon/sysmonvar.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_socthermreg.h> 44 #include <arm/nvidia/tegra_var.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define FUSE_TSENSOR_CALIB_CP_TS_BASE __BITS(12,0) 49 #define FUSE_TSENSOR_CALIB_FT_TS_BASE __BITS(25,13) 50 51 #define FUSE_TSENSOR8_CALIB_REG 0x180 52 #define FUSE_TSENSOR8_CALIB_CP_TS_BASE __BITS(9,0) 53 #define FUSE_TSENSOR8_CALIB_FT_TS_BASE __BITS(20,10) 54 55 #define FUSE_SPARE_REALIGNMENT_REG 0x1fc 56 #define FUSE_SPARE_REALIGNMENT_CP __BITS(5,0) 57 #define FUSE_SPARE_REALIGNMENT_FT __BITS(25,21) 58 59 static int tegra_soctherm_match(device_t, cfdata_t, void *); 60 static void tegra_soctherm_attach(device_t, device_t, void *); 61 62 struct tegra_soctherm_config { 63 uint32_t init_pdiv; 64 uint32_t init_hotspot_off; 65 uint32_t nominal_calib_ft; 66 uint32_t nominal_calib_cp; 67 uint32_t tall; 68 uint32_t tsample; 69 uint32_t tiddq_en; 70 uint32_t ten_count; 71 uint32_t pdiv; 72 uint32_t tsample_ate; 73 uint32_t pdiv_ate; 74 }; 75 76 static const struct tegra_soctherm_config tegra124_soctherm_config = { 77 .init_pdiv = 0x8888, 78 .init_hotspot_off = 0x60600, 79 .nominal_calib_ft = 105, 80 .nominal_calib_cp = 25, 81 .tall = 16300, 82 .tsample = 120, 83 .tiddq_en = 1, 84 .ten_count = 1, 85 .pdiv = 8, 86 .tsample_ate = 480, 87 .pdiv_ate = 8 88 }; 89 90 struct tegra_soctherm_sensor { 91 envsys_data_t s_data; 92 u_int s_base; 93 u_int s_fuse; 94 int s_fuse_corr_alpha; 95 int s_fuse_corr_beta; 96 int16_t s_therm_a; 97 int16_t s_therm_b; 98 }; 99 100 static const struct tegra_soctherm_sensor tegra_soctherm_sensors[] = { 101 { .s_data = { .desc = "CPU0" }, .s_base = 0x0c0, .s_fuse = 0x098, 102 .s_fuse_corr_alpha = 1135400, .s_fuse_corr_beta = -6266900 }, 103 { .s_data = { .desc = "CPU1" }, .s_base = 0x0e0, .s_fuse = 0x084, 104 .s_fuse_corr_alpha = 1122220, .s_fuse_corr_beta = -5700700 }, 105 { .s_data = { .desc = "CPU2" }, .s_base = 0x100, .s_fuse = 0x088, 106 .s_fuse_corr_alpha = 1127000, .s_fuse_corr_beta = -6768200 }, 107 { .s_data = { .desc = "CPU3" }, .s_base = 0x120, .s_fuse = 0x12c, 108 .s_fuse_corr_alpha = 1110900, .s_fuse_corr_beta = -6232000 }, 109 { .s_data = { .desc = "MEM0" }, .s_base = 0x140, .s_fuse = 0x158, 110 .s_fuse_corr_alpha = 1122300, .s_fuse_corr_beta = -5936400 }, 111 { .s_data = { .desc = "MEM1" }, .s_base = 0x160, .s_fuse = 0x15c, 112 .s_fuse_corr_alpha = 1145700, .s_fuse_corr_beta = -7124600 }, 113 { .s_data = { .desc = "GPU" }, .s_base = 0x180, .s_fuse = 0x154, 114 .s_fuse_corr_alpha = 1120100, .s_fuse_corr_beta = -6000500 }, 115 { .s_data = { .desc = "PLLX" }, .s_base = 0x1a0, .s_fuse = 0x160, 116 .s_fuse_corr_alpha = 1106500, .s_fuse_corr_beta = -6729300 }, 117 }; 118 119 struct tegra_soctherm_softc { 120 device_t sc_dev; 121 bus_space_tag_t sc_bst; 122 bus_space_handle_t sc_bsh; 123 struct clk *sc_clk_tsensor; 124 struct clk *sc_clk_soctherm; 125 struct fdtbus_reset *sc_rst_soctherm; 126 127 struct sysmon_envsys *sc_sme; 128 struct tegra_soctherm_sensor *sc_sensors; 129 const struct tegra_soctherm_config *sc_config; 130 131 uint32_t sc_base_cp; 132 uint32_t sc_base_ft; 133 int32_t sc_actual_temp_cp; 134 int32_t sc_actual_temp_ft; 135 }; 136 137 static int tegra_soctherm_init_clocks(struct tegra_soctherm_softc *); 138 static void tegra_soctherm_init_sensors(device_t); 139 static void tegra_soctherm_init_sensor(struct tegra_soctherm_softc *, 140 struct tegra_soctherm_sensor *); 141 static void tegra_soctherm_refresh(struct sysmon_envsys *, envsys_data_t *); 142 static int tegra_soctherm_decodeint(uint32_t, uint32_t); 143 static int64_t tegra_soctherm_divide(int64_t, int64_t); 144 145 CFATTACH_DECL_NEW(tegra_soctherm, sizeof(struct tegra_soctherm_softc), 146 tegra_soctherm_match, tegra_soctherm_attach, NULL, NULL); 147 148 #define SOCTHERM_READ(sc, reg) \ 149 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 150 #define SOCTHERM_WRITE(sc, reg, val) \ 151 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 152 #define SOCTHERM_SET_CLEAR(sc, reg, set, clr) \ 153 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr)) 154 155 #define SENSOR_READ(sc, s, reg) \ 156 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg)) 157 #define SENSOR_WRITE(sc, s, reg, val) \ 158 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg), (val)) 159 #define SENSOR_SET_CLEAR(sc, s, reg, set, clr) \ 160 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg), (set), (clr)) 161 162 static const struct device_compatible_entry compat_data[] = { 163 { .compat = "nvidia,tegra124-soctherm", 164 .data = &tegra124_soctherm_config }, 165 166 DEVICE_COMPAT_EOL 167 }; 168 169 static int 170 tegra_soctherm_match(device_t parent, cfdata_t cf, void *aux) 171 { 172 struct fdt_attach_args * const faa = aux; 173 174 return of_compatible_match(faa->faa_phandle, compat_data); 175 } 176 177 static void 178 tegra_soctherm_attach(device_t parent, device_t self, void *aux) 179 { 180 struct tegra_soctherm_softc * const sc = device_private(self); 181 struct fdt_attach_args * const faa = aux; 182 const int phandle = faa->faa_phandle; 183 bus_addr_t addr; 184 bus_size_t size; 185 int error; 186 187 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 188 aprint_error(": couldn't get registers\n"); 189 return; 190 } 191 sc->sc_clk_tsensor = fdtbus_clock_get(phandle, "tsensor"); 192 if (sc->sc_clk_tsensor == NULL) { 193 aprint_error(": couldn't get clock tsensor\n"); 194 return; 195 } 196 sc->sc_clk_soctherm = fdtbus_clock_get(phandle, "soctherm"); 197 if (sc->sc_clk_soctherm == NULL) { 198 aprint_error(": couldn't get clock soctherm\n"); 199 return; 200 } 201 sc->sc_rst_soctherm = fdtbus_reset_get(phandle, "soctherm"); 202 if (sc->sc_rst_soctherm == NULL) { 203 aprint_error(": couldn't get reset soctherm\n"); 204 return; 205 } 206 207 sc->sc_dev = self; 208 sc->sc_bst = faa->faa_bst; 209 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 210 if (error) { 211 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 212 return; 213 } 214 215 aprint_naive("\n"); 216 aprint_normal(": SOC_THERM\n"); 217 218 sc->sc_config = of_compatible_lookup(phandle, compat_data)->data; 219 if (sc->sc_config == NULL) { 220 aprint_error_dev(self, "unsupported SoC\n"); 221 return; 222 } 223 224 if (tegra_soctherm_init_clocks(sc) != 0) 225 return; 226 227 config_defer(self, tegra_soctherm_init_sensors); 228 } 229 230 static int 231 tegra_soctherm_init_clocks(struct tegra_soctherm_softc *sc) 232 { 233 int error; 234 235 fdtbus_reset_assert(sc->sc_rst_soctherm); 236 237 error = clk_set_rate(sc->sc_clk_soctherm, 51000000); 238 if (error) { 239 aprint_error_dev(sc->sc_dev, 240 "couldn't set soctherm rate: %d\n", error); 241 return error; 242 } 243 244 error = clk_set_rate(sc->sc_clk_tsensor, 400000); 245 if (error) { 246 aprint_error_dev(sc->sc_dev, 247 "couldn't set tsensor rate: %d\n", error); 248 return error; 249 } 250 251 error = clk_enable(sc->sc_clk_tsensor); 252 if (error) { 253 aprint_error_dev(sc->sc_dev, "couldn't enable tsensor: %d\n", 254 error); 255 return error; 256 } 257 258 error = clk_enable(sc->sc_clk_soctherm); 259 if (error) { 260 aprint_error_dev(sc->sc_dev, "couldn't enable soctherm: %d\n", 261 error); 262 return error; 263 } 264 265 fdtbus_reset_deassert(sc->sc_rst_soctherm); 266 267 return 0; 268 } 269 270 static void 271 tegra_soctherm_init_sensors(device_t dev) 272 { 273 struct tegra_soctherm_softc * const sc = device_private(dev); 274 const struct tegra_soctherm_config *config = sc->sc_config; 275 const u_int nsensors = __arraycount(tegra_soctherm_sensors); 276 const size_t len = sizeof(*sc->sc_sensors) * nsensors; 277 uint32_t val; 278 u_int n; 279 280 val = tegra_fuse_read(FUSE_TSENSOR8_CALIB_REG); 281 sc->sc_base_cp = __SHIFTOUT(val, FUSE_TSENSOR8_CALIB_CP_TS_BASE); 282 sc->sc_base_ft = __SHIFTOUT(val, FUSE_TSENSOR8_CALIB_FT_TS_BASE); 283 val = tegra_fuse_read(FUSE_SPARE_REALIGNMENT_REG); 284 const int calib_cp = tegra_soctherm_decodeint(val, 285 FUSE_SPARE_REALIGNMENT_CP); 286 const int calib_ft = tegra_soctherm_decodeint(val, 287 FUSE_SPARE_REALIGNMENT_FT); 288 sc->sc_actual_temp_cp = 2 * config->nominal_calib_cp + calib_cp; 289 sc->sc_actual_temp_ft = 2 * config->nominal_calib_ft + calib_ft; 290 291 sc->sc_sme = sysmon_envsys_create(); 292 sc->sc_sme->sme_name = device_xname(sc->sc_dev); 293 sc->sc_sme->sme_cookie = sc; 294 sc->sc_sme->sme_refresh = tegra_soctherm_refresh; 295 296 sc->sc_sensors = kmem_zalloc(len, KM_SLEEP); 297 for (n = 0; n < nsensors; n++) { 298 sc->sc_sensors[n] = tegra_soctherm_sensors[n]; 299 tegra_soctherm_init_sensor(sc, &sc->sc_sensors[n]); 300 } 301 302 SOCTHERM_WRITE(sc, SOC_THERM_TSENSOR_PDIV_REG, config->init_pdiv); 303 SOCTHERM_WRITE(sc, SOC_THERM_TSENSOR_HOTSPOT_OFF_REG, 304 config->init_hotspot_off); 305 306 sysmon_envsys_register(sc->sc_sme); 307 } 308 309 static void 310 tegra_soctherm_init_sensor(struct tegra_soctherm_softc *sc, 311 struct tegra_soctherm_sensor *s) 312 { 313 const struct tegra_soctherm_config *config = sc->sc_config; 314 int64_t temp_a, temp_b, tmp; 315 uint32_t val; 316 317 val = tegra_fuse_read(s->s_fuse); 318 const int calib_cp = tegra_soctherm_decodeint(val, 319 FUSE_TSENSOR_CALIB_CP_TS_BASE); 320 const int calib_ft = tegra_soctherm_decodeint(val, 321 FUSE_TSENSOR_CALIB_FT_TS_BASE); 322 const int actual_cp = sc->sc_base_cp * 64 + calib_cp; 323 const int actual_ft = sc->sc_base_ft * 32 + calib_ft; 324 325 const int64_t d_sensor = actual_ft - actual_cp; 326 const int64_t d_temp = sc->sc_actual_temp_ft - sc->sc_actual_temp_cp; 327 const int mult = config->pdiv * config->tsample_ate; 328 const int div = config->tsample * config->pdiv_ate; 329 330 temp_a = tegra_soctherm_divide(d_temp * 0x2000 * mult, 331 d_sensor * div); 332 tmp = (int64_t)actual_ft * sc->sc_actual_temp_cp - 333 (int64_t)actual_cp * sc->sc_actual_temp_ft; 334 temp_b = tegra_soctherm_divide(tmp, d_sensor); 335 temp_a = tegra_soctherm_divide( 336 temp_a * s->s_fuse_corr_alpha, 1000000); 337 temp_b = (uint16_t)tegra_soctherm_divide( 338 temp_b * s->s_fuse_corr_alpha + s->s_fuse_corr_beta, 1000000); 339 340 s->s_therm_a = (int16_t)temp_a; 341 s->s_therm_b = (int16_t)temp_b; 342 343 SENSOR_SET_CLEAR(sc, s, SOC_THERM_TSENSOR_CONFIG0_OFFSET, 344 SOC_THERM_TSENSOR_CONFIG0_STATUS_CLR | 345 SOC_THERM_TSENSOR_CONFIG0_STOP, 0); 346 SENSOR_WRITE(sc, s, SOC_THERM_TSENSOR_CONFIG0_OFFSET, 347 __SHIFTIN(config->tall, SOC_THERM_TSENSOR_CONFIG0_TALL) | 348 SOC_THERM_TSENSOR_CONFIG0_STOP); 349 350 SENSOR_WRITE(sc, s, SOC_THERM_TSENSOR_CONFIG1_OFFSET, 351 __SHIFTIN(config->tsample - 1, SOC_THERM_TSENSOR_CONFIG1_TSAMPLE) | 352 __SHIFTIN(config->tiddq_en, SOC_THERM_TSENSOR_CONFIG1_TIDDQ_EN) | 353 __SHIFTIN(config->ten_count, SOC_THERM_TSENSOR_CONFIG1_TEN_COUNT) | 354 SOC_THERM_TSENSOR_CONFIG1_TEMP_ENABLE); 355 356 SENSOR_WRITE(sc, s, SOC_THERM_TSENSOR_CONFIG2_OFFSET, 357 __SHIFTIN((uint16_t)s->s_therm_a, 358 SOC_THERM_TSENSOR_CONFIG2_THERM_A) | 359 __SHIFTIN((uint16_t)s->s_therm_b, 360 SOC_THERM_TSENSOR_CONFIG2_THERM_B)); 361 362 SENSOR_SET_CLEAR(sc, s, SOC_THERM_TSENSOR_CONFIG0_OFFSET, 363 0, SOC_THERM_TSENSOR_CONFIG0_STOP); 364 365 s->s_data.units = ENVSYS_STEMP; 366 s->s_data.state = ENVSYS_SINVALID; 367 sysmon_envsys_sensor_attach(sc->sc_sme, &s->s_data); 368 } 369 370 static void 371 tegra_soctherm_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 372 { 373 struct tegra_soctherm_softc * const sc = sme->sme_cookie; 374 struct tegra_soctherm_sensor *s = (struct tegra_soctherm_sensor *)edata; 375 uint32_t status; 376 377 status = SENSOR_READ(sc, s, SOC_THERM_TSENSOR_STATUS1_OFFSET); 378 if (status & SOC_THERM_TSENSOR_STATUS1_TEMP_VALID) { 379 const u_int temp = __SHIFTOUT(status, 380 SOC_THERM_TSENSOR_STATUS1_TEMP); 381 int64_t val = ((temp >> 8) & 0xff) * 1000000; 382 if (temp & 0x80) 383 val += 500000; 384 if (temp & 0x02) 385 val = -val; 386 edata->value_cur = val + 273150000; 387 edata->state = ENVSYS_SVALID; 388 } else { 389 edata->state = ENVSYS_SINVALID; 390 } 391 } 392 393 static int 394 tegra_soctherm_decodeint(uint32_t val, uint32_t bitmask) 395 { 396 const uint32_t v = __SHIFTOUT(val, bitmask); 397 const int bits = popcount32(bitmask); 398 int ret = v << (32 - bits); 399 return ret >> (32 - bits); 400 } 401 402 static int64_t 403 tegra_soctherm_divide(int64_t num, int64_t denom) 404 { 405 int64_t ret = ((num << 16) * 2 + 1) / (2 * denom); 406 return ret >> 16; 407 } 408
Indexes created Mon Sep 22 13:09:51 GMT 2025