| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_rv740_dpm.c | 170 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); local
177 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
259 u32 clk_v = 0x40000 * ss.percentage * local
263 mpll_ss1 |= CLKV(clk_v);
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| radeon_rv730_dpm.c | 102 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000); local
109 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
178 u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000); local
185 mpll_ss |= CLK_V(clk_v);
|
| radeon_r600_dpm.c | 973 ATOM_PPLIB_Clock_Voltage_Limit_Table *clk_v = local
977 if (clk_v->ucNumEntries) {
979 le16_to_cpu(clk_v->entries[0].usSclkLow) |
980 (clk_v->entries[0].ucSclkHigh << 16);
982 le16_to_cpu(clk_v->entries[0].usMclkLow) |
983 (clk_v->entries[0].ucMclkHigh << 16);
985 le16_to_cpu(clk_v->entries[0].usVddc);
987 le16_to_cpu(clk_v->entries[0].usVddci);
|
| radeon_rv6xx_dpm.c | 327 u32 index, u32 clk_v)
330 CLKV(clk_v), ~CLKV_MASK);
351 u32 clk_v)
353 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK);
560 u32 vco_freq, clk_v, clk_s; local
571 clk_v = rv6xx_calculate_spread_spectrum_clk_v(vco_freq,
580 rv6xx_set_engine_spread_spectrum_clk_v(rdev, level, clk_v);
663 u32 vco_freq = 0, clk_v, clk_s; local
689 clk_v = rv6xx_calculate_spread_spectrum_clk_v(vco_freq,
698 rv6xx_set_memory_spread_spectrum_clk_v(rdev, clk_v);
[all...] |
| radeon_ni_dpm.c | 2051 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); local
2058 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
2103 u32 clk_v; local
2123 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2127 clk_v >>= 6;
2138 if (clk_v & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2148 tmp = ((clk_v << SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2249 u32 clk_v = ss.percentage * local
2253 mpll_ss1 |= CLKV(clk_v);
[all...] |
| radeon_cypress_dpm.c | 568 u32 clk_v = ss.percentage * local
572 mpll_ss1 |= CLKV(clk_v);
|
| radeon_rv770_dpm.c | 549 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000); local
556 cg_spll_spread_spectrum_2 |= CLKV(clk_v);
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| radeon_si_dpm.c | 2858 u32 clk_s, clk_v; local
2879 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2883 clk_v >>= 6;
2891 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2901 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
4833 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); local
4840 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
|
| radeon_ci_dpm.c | 3200 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); local
3207 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dpm.c | 380 ATOM_PPLIB_Clock_Voltage_Limit_Table *clk_v = local
384 if (clk_v->ucNumEntries) {
386 le16_to_cpu(clk_v->entries[0].usSclkLow) |
387 (clk_v->entries[0].ucSclkHigh << 16);
389 le16_to_cpu(clk_v->entries[0].usMclkLow) |
390 (clk_v->entries[0].ucMclkHigh << 16);
392 le16_to_cpu(clk_v->entries[0].usVddc);
394 le16_to_cpu(clk_v->entries[0].usVddci);
|
| amdgpu_si_dpm.c | 2958 u32 clk_s, clk_v; local
2978 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2982 clk_v >>= 6;
2990 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
3000 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
5297 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); local
5304 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_fiji_smumgr.c | 921 uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage * local
929 CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
|
| amdgpu_ci_smumgr.c | 352 uint32_t clk_v = 4 * ss_info.speed_spectrum_percentage * local
360 CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
|
