| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/ |
| amdgpu_command_table.c | 111 struct bp_encoder_control *cntl);
115 struct bp_encoder_control *cntl);
119 struct bp_encoder_control *cntl);
148 struct bp_encoder_control *cntl);
151 struct bp_encoder_control *cntl);
154 struct bp_encoder_control *cntl);
175 struct bp_encoder_control *cntl)
180 if (cntl != NULL)
181 switch (cntl->engine_id) {
185 cmd_tbl->encoder_control_dig1(bp, cntl);
[all...] |
| amdgpu_command_table2.c | 95 struct bp_encoder_control *cntl);
99 struct bp_encoder_control *cntl);
134 struct bp_encoder_control *cntl)
139 params.digid = (uint8_t)(cntl->engine_id);
140 params.action = bp->cmd_helper->encoder_action_to_atom(cntl->action);
142 params.pclk_10khz = cntl->pixel_clock / 10;
145 cntl->signal,
146 cntl->enable_dp_audio));
147 params.lanenum = (uint8_t)(cntl->lanes_number);
149 switch (cntl->color_depth)
[all...] |
| command_table.h | 89 struct bp_external_encoder_control *cntl);
|
| command_table2.h | 89 struct bp_external_encoder_control *cntl);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_link_encoder.c | 131 struct bp_transmitter_control *cntl)
136 result = bp->funcs->transmitter_control(bp, cntl);
835 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_link_encoder_hw_init
838 cntl.action = TRANSMITTER_CONTROL_INIT;
839 cntl.engine_id = ENGINE_ID_UNKNOWN;
840 cntl.transmitter = enc110->base.transmitter;
841 cntl.connector_obj_id = enc110->base.connector;
842 cntl.lanes_number = LANE_COUNT_FOUR;
843 cntl.coherent = false;
844 cntl.hpd_sel = enc110->base.hpd_source
928 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_link_encoder_enable_tmds_output
964 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_link_encoder_enable_lvds_output
996 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_link_encoder_enable_dp_output
1035 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_link_encoder_enable_dp_mst_output
1075 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_link_encoder_disable_output
1120 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_link_encoder_dp_set_lane_settings
[all...] |
| amdgpu_dce_stream_encoder.c | 564 struct bp_encoder_control cntl = {0}; local in function:dce110_stream_encoder_hdmi_set_stream_attribute
566 cntl.action = ENCODER_CONTROL_SETUP;
567 cntl.engine_id = enc110->base.id;
568 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
569 cntl.enable_dp_audio = enable_audio;
570 cntl.pixel_clock = actual_pix_clk_khz;
571 cntl.lanes_number = LANE_COUNT_FOUR;
574 enc110->base.bp, &cntl) != BP_RESULT_OK)
677 struct bp_encoder_control cntl = {0}; local in function:dce110_stream_encoder_dvi_set_stream_attribute
679 cntl.action = ENCODER_CONTROL_SETUP
702 struct bp_encoder_control cntl = {0}; local in function:dce110_stream_encoder_lvds_set_stream_attribute
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_link_encoder.c | 103 struct bp_transmitter_control *cntl)
108 result = bp->funcs->transmitter_control(bp, cntl);
828 struct bp_transmitter_control cntl = { 0 }; local in function:dcn10_link_encoder_hw_init
831 cntl.action = TRANSMITTER_CONTROL_INIT;
832 cntl.engine_id = ENGINE_ID_UNKNOWN;
833 cntl.transmitter = enc10->base.transmitter;
834 cntl.connector_obj_id = enc10->base.connector;
835 cntl.lanes_number = LANE_COUNT_FOUR;
836 cntl.coherent = false;
837 cntl.hpd_sel = enc10->base.hpd_source
922 struct bp_transmitter_control cntl = { 0 }; local in function:dcn10_link_encoder_enable_tmds_output
958 struct bp_transmitter_control cntl = { 0 }; local in function:dcn10_link_encoder_enable_dp_output
997 struct bp_transmitter_control cntl = { 0 }; local in function:dcn10_link_encoder_enable_dp_mst_output
1037 struct bp_transmitter_control cntl = { 0 }; local in function:dcn10_link_encoder_disable_output
1086 struct bp_transmitter_control cntl = { 0 }; local in function:dcn10_link_encoder_dp_set_lane_settings
[all...] |
| amdgpu_dcn10_stream_encoder.c | 502 struct bp_encoder_control cntl = {0}; local in function:enc1_stream_encoder_hdmi_set_stream_attribute
504 cntl.action = ENCODER_CONTROL_SETUP;
505 cntl.engine_id = enc1->base.id;
506 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
507 cntl.enable_dp_audio = enable_audio;
508 cntl.pixel_clock = actual_pix_clk_khz;
509 cntl.lanes_number = LANE_COUNT_FOUR;
512 enc1->base.bp, &cntl) != BP_RESULT_OK)
608 struct bp_encoder_control cntl = {0}; local in function:enc1_stream_encoder_dvi_set_stream_attribute
610 cntl.action = ENCODER_CONTROL_SETUP
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| amdgpu_dce100_hw_sequencer.c | 84 enum bp_pipe_control_action cntl; local in function:dce100_enable_display_power_gating
88 cntl = ASIC_PIPE_INIT;
90 cntl = ASIC_PIPE_ENABLE;
92 cntl = ASIC_PIPE_DISABLE;
97 dcb, controller_id + 1, cntl);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_hw_sequencer.c | 125 enum bp_pipe_control_action cntl; local in function:dce112_enable_display_power_gating
132 cntl = ASIC_PIPE_INIT;
134 cntl = ASIC_PIPE_ENABLE;
136 cntl = ASIC_PIPE_DISABLE;
141 dcb, controller_id + 1, cntl);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_hw_sequencer.c | 164 enum bp_pipe_control_action cntl;
171 cntl = ASIC_PIPE_INIT;
173 cntl = ASIC_PIPE_ENABLE;
175 cntl = ASIC_PIPE_DISABLE;
180 dcb, controller_id + 1, cntl);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| kfd_dbgdev.c | 238 union TCP_WATCH_CNTL_BITS *cntl,
246 cntl->u32All = 0;
249 cntl->bitfields.mask =
253 cntl->bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
262 cntl->bitfields.mode = adw_info->watch_mode[index];
263 cntl->bitfields.vmid = (uint32_t) vmid;
265 cntl->u32All |= ADDRESS_WATCH_REG_CNTL_ATC_BIT;
267 pr_debug("\t\t%20s %08x\n", "set reg mask :", cntl->bitfields.mask);
279 union TCP_WATCH_CNTL_BITS cntl; local in function:dbgdev_address_watch_nodiq
293 cntl.u32All = 0
346 union TCP_WATCH_CNTL_BITS cntl; local in function:dbgdev_address_watch_diq
[all...] |
| /src/sys/arch/arm/amlogic/ |
| meson8b_clkc.c | 123 uint32_t cntl = CLK_READ(sc, HHI_SYS_PLL_CNTL); local in function:meson8b_clkc_pll_sys_set_rate
150 cntl &= ~HHI_SYS_PLL_CNTL_MUL;
151 cntl |= __SHIFTIN(new_mul, HHI_SYS_PLL_CNTL_MUL);
152 cntl &= ~HHI_SYS_PLL_CNTL_DIV;
153 cntl |= __SHIFTIN(new_div, HHI_SYS_PLL_CNTL_DIV);
154 cntl &= ~HHI_SYS_PLL_CNTL_OD;
155 cntl |= __SHIFTIN(new_od, HHI_SYS_PLL_CNTL_OD);
165 CLK_WRITE(sc, HHI_SYS_PLL_CNTL, cntl);
|
| meson_sdhc.c | 597 uint32_t cntl; local in function:meson_sdhc_bus_width
599 cntl = SDHC_READ(sc, SD_CNTL_REG);
600 cntl &= ~SD_CNTL_DAT_TYPE;
603 cntl |= __SHIFTIN(0, SD_CNTL_DAT_TYPE);
606 cntl |= __SHIFTIN(1, SD_CNTL_DAT_TYPE);
609 cntl |= __SHIFTIN(2, SD_CNTL_DAT_TYPE);
615 SDHC_WRITE(sc, SD_CNTL_REG, cntl);
630 uint32_t cmdval = 0, cntl, srst, pdma, ictl; local in function:meson_sdhc_exec_command
664 cntl = SDHC_READ(sc, SD_CNTL_REG);
665 cntl &= ~SD_CNTL_PACK_LEN
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_amdkfd_gfx_v7.c | 589 union TCP_WATCH_CNTL_BITS cntl; local in function:kgd_address_watch_disable
592 cntl.u32All = 0;
594 cntl.bitfields.valid = 0;
595 cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
596 cntl.bitfields.atc = 1;
601 ADDRESS_WATCH_REG_CNTL], cntl.u32All);
613 union TCP_WATCH_CNTL_BITS cntl; local in function:kgd_address_watch_execute
615 cntl.u32All = cntl_val;
618 cntl.bitfields.valid = 0;
620 ADDRESS_WATCH_REG_CNTL], cntl.u32All)
[all...] |
| kv_dpm.h | 87 u32 cntl; member in struct:kv_lcac_config_reg
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_bios_types.h | 99 struct bp_encoder_control *cntl);
102 struct bp_transmitter_control *cntl);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_hw_sequencer.c | 206 enum bp_pipe_control_action cntl; local in function:dce110_enable_display_power_gating
214 cntl = ASIC_PIPE_INIT;
216 cntl = ASIC_PIPE_ENABLE;
218 cntl = ASIC_PIPE_DISABLE;
226 dcb, controller_id + 1, cntl);
727 struct bp_transmitter_control *cntl)
731 result = bios->funcs->transmitter_control(bios, cntl);
814 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_edp_power_control
858 cntl.action = power_up ?
861 cntl.transmitter = link->link_enc->transmitter
896 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_edp_backlight_control
[all...] |
| /src/libexec/rlogind/ |
| rlogind.c | 455 char cntl; local in function:protocol
492 cc = read(p, &cntl, 1);
493 if (cc == 1 && pkcontrol(cntl)) {
494 cntl |= oobdata[0];
495 send(f, &cntl, 1, MSG_OOB);
496 if (cntl & TIOCPKT_FLUSHWRITE)
|
| /src/sys/dev/dec/ |
| if_le_dec.c | 108 #define LERDWR(cntl, src, dst) { (dst) = (src); tc_mb(); }
|
| /src/sys/arch/mips/adm5120/dev/ |
| if_admswvar.h | 189 __desc->cntl = 0; \
206 __desc->cntl = 0; \
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| kv_dpm.h | 61 u32 cntl; member in struct:kv_lcac_config_reg
|
| /src/sys/dev/ieee1394/ |
| fwohcireg.h | 193 fwohcireg_t cntl; member in struct:ohci_dma
220 fwohcireg_t cntl; member in struct:ohci_itdma
293 fwohcireg_t phy_access; /* PHY cntl 0xec */
|
| /src/sys/dev/ic/ |
| advlib.c | 402 eep_config->cntl = 0xBFFF;
428 sc->dvc_cntl = eep_config->cntl;
1425 printf("cntl = 0x%x\n", eep_config->cntl);
1560 if ((scsiq->cntl & ASC_QC_SG_HEAD) != 0) {
1609 if ((scsiq->cntl & (ASC_QC_DATA_IN | ASC_QC_DATA_OUT)) == 0) {
1821 scsiq->cntl = LO_BYTE(_val);
2284 scsiq->q1.cntl |= (ASC_QC_MSG_OUT | ASC_QC_URGENT);
2291 if ((scsiq->q1.cntl & ASC_QC_SG_HEAD) != 0) {
2304 scsiq->q1.cntl &= ~(ASC_QC_SG_HEAD | ASC_QC_SG_SWAP_QUEUE)
[all...] |
| /src/sys/arch/hppa/gsc/ |
| harmony.c | 214 uint32_t cntl; local in function:harmony_attach
231 cntl = READ_REG(sc, HARMONY_ID);
232 switch ((cntl & ID_REV_MASK)) {
239 (cntl & ID_REV_MASK) >> ID_REV_SHIFT);
313 cntl = READ_REG(sc, HARMONY_CNTL);
314 rev = (cntl & CNTL_CODEC_REV_MASK) >> CNTL_CODEC_REV_SHIFT;
1181 /* XXX leave these bits alone or the chip will not come out of CNTL */
|
