| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_vega10_powertune.c | 804 static int vega10_program_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs, enum vega10_didt_config_reg_type reg_type)
808 PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config register table!", return -EINVAL);
810 while (config_regs->offset != 0xFFFFFFFF) {
813 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
814 data &= ~config_regs->mask;
815 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
816 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data);
819 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset)
[all...] |
| amdgpu_smu7_powertune.c | 903 const struct gpu_pt_config_reg *config_regs = cac_config_regs; local in function:smu7_program_pt_config_registers
907 PP_ASSERT_WITH_CODE((config_regs != NULL), "Invalid config register table.", return -EINVAL);
909 while (config_regs->offset != 0xFFFFFFFF) {
910 if (config_regs->type == GPU_CONFIGREG_CACHE)
911 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
913 switch (config_regs->type) {
915 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset);
919 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_kv_dpm.c | 418 const struct kv_pt_config_reg *config_regs = cac_config_regs; local in function:kv_program_pt_config_registers
422 if (config_regs == NULL)
425 while (config_regs->offset != 0xFFFFFFFF) {
426 if (config_regs->type == KV_CONFIGREG_CACHE) {
427 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
429 switch (config_regs->type) {
431 data = RREG32_SMC(config_regs->offset);
434 data = RREG32_DIDT(config_regs->offset)
[all...] |
| amdgpu_si_dpm.c | 2845 const struct si_cac_config_reg *config_regs = cac_config_regs; local in function:si_program_cac_config_registers
2848 if (!config_regs)
2851 while (config_regs->offset != 0xFFFFFFFF) {
2852 switch (config_regs->type) {
2854 offset = SMC_CG_IND_START + config_regs->offset;
2859 data = RREG32(config_regs->offset);
2863 data &= ~config_regs->mask;
2864 data |= ((config_regs->value << config_regs->shift) & config_regs->mask)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_kv_dpm.c | 291 const struct kv_pt_config_reg *config_regs = cac_config_regs; local in function:kv_program_pt_config_registers
295 if (config_regs == NULL)
298 while (config_regs->offset != 0xFFFFFFFF) {
299 if (config_regs->type == KV_CONFIGREG_CACHE) {
300 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
302 switch (config_regs->type) {
304 data = RREG32_SMC(config_regs->offset);
307 data = RREG32_DIDT(config_regs->offset)
[all...] |
| radeon_ci_dpm.c | 575 const struct ci_pt_config_reg *config_regs = cac_config_regs; local in function:ci_program_pt_config_registers
579 if (config_regs == NULL)
582 while (config_regs->offset != 0xFFFFFFFF) {
583 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
584 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
586 switch (config_regs->type) {
588 data = RREG32_SMC(config_regs->offset);
591 data = RREG32_DIDT(config_regs->offset)
[all...] |
| radeon_si_dpm.c | 2745 const struct si_cac_config_reg *config_regs = cac_config_regs; local in function:si_program_cac_config_registers
2748 if (!config_regs)
2751 while (config_regs->offset != 0xFFFFFFFF) {
2752 switch (config_regs->type) {
2754 offset = SMC_CG_IND_START + config_regs->offset;
2759 data = RREG32(config_regs->offset << 2);
2763 data &= ~config_regs->mask;
2764 data |= ((config_regs->value << config_regs->shift) & config_regs->mask)
[all...] |
