| /src/sys/external/bsd/drm2/dist/include/drm/ |
| drm_atomic.h | 317 * @crtcs: pointer to array of CRTC pointers
354 struct __drm_crtcs_state *crtcs; member in struct:drm_atomic_state
496 return state->crtcs[drm_crtc_index(crtc)].state;
511 return state->crtcs[drm_crtc_index(crtc)].old_state;
525 return state->crtcs[drm_crtc_index(crtc)].new_state;
756 * for_each_oldnew_crtc_in_state - iterate over all CRTCs in an atomic update
763 * This iterates over all CRTCs in an atomic update, tracking both old and
771 for_each_if ((__state)->crtcs[__i].ptr && \
772 ((crtc) = (__state)->crtcs[__i].ptr, \
774 (old_crtc_state) = (__state)->crtcs[__i].old_state,
[all...] |
| /src/sys/external/bsd/drm2/drm/ |
| drm_lease.c | 107 * drm_lease_filter_crtcs(file, crtcs)
112 drm_lease_filter_crtcs(struct drm_file *file, uint32_t crtcs)
114 return crtcs;
|
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_client_modeset.c | 500 struct drm_crtc **crtcs, *crtc; local
515 crtcs = kcalloc(connector_count, sizeof(*crtcs), GFP_KERNEL);
516 if (!crtcs)
550 crtcs[n] = crtc;
551 memcpy(crtcs, best_crtcs, n * sizeof(*crtcs));
553 crtcs, modes, n + 1, width, height);
556 memcpy(best_crtcs, crtcs, connector_count * sizeof(*crtcs));
777 struct drm_crtc **crtcs; local
[all...] |
| drm_atomic.c | 76 kfree(state->crtcs);
101 state->crtcs = kcalloc(dev->mode_config.num_crtc,
102 sizeof(*state->crtcs), GFP_KERNEL);
103 if (!state->crtcs)
181 struct drm_crtc *crtc = state->crtcs[i].ptr;
187 state->crtcs[i].state);
189 state->crtcs[i].ptr = NULL;
190 state->crtcs[i].state = NULL;
191 state->crtcs[i].old_state = NULL;
192 state->crtcs[i].new_state = NULL
[all...] |
| drm_atomic_helper.c | 916 * Only CRTCs and planes have check callbacks, so for any additional (global)
1095 * connectors, encoders and CRTCs. It also updates the timestamping constants
1309 /* Need to filter out CRTCs where only planes change. */
1422 * drm_atomic_helper_wait_for_vblanks - wait for vblank on CRTCs
1427 * CRTCs (ie. before cleaning up old framebuffers using
1428 * drm_atomic_helper_cleanup_planes()). It will only wait on CRTCs where the
1461 old_state->crtcs[i].last_vblank_count = drm_crtc_vblank_count(crtc);
1475 if (old_state->crtcs[i].last_vblank_count !=
1486 (old_state->crtcs[i].last_vblank_count !=
1492 old_state->crtcs[i].last_vblank_count !
[all...] |
| drm_atomic_uapi.c | 348 state->crtcs[drm_crtc_index(crtc)].out_fence_ptr = fence_ptr;
356 fence_ptr = state->crtcs[drm_crtc_index(crtc)].out_fence_ptr;
357 state->crtcs[drm_crtc_index(crtc)].out_fence_ptr = NULL;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_virtual.c | 241 adev->mode_info.crtcs[index] = amdgpu_crtc;
391 /* allocate crtcs, encoders, connectors */
416 /* clear crtcs pointer to avoid dce irq finish routine access freed data */
417 memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS);
473 if (adev->mode_info.crtcs[i])
651 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
710 if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) {
715 if (state && !adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
717 hrtimer_init(&adev->mode_info.crtcs[crtc]->vblank_timer
[all...] |
| amdgpu_dce_v6_0.c | 198 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
508 u32 num_heads; /* number of active crtcs */
1011 * of crtcs. Ideally for multiple large displays we'd assign them to
1012 * non-linked crtcs for maximum line buffer allocation.
1076 if (adev->mode_info.crtcs[i]->base.enabled)
1080 mode0 = &adev->mode_info.crtcs[i]->base.mode;
1081 mode1 = &adev->mode_info.crtcs[i+1]->base.mode;
1082 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1);
1083 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads);
1084 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0)
[all...] |
| amdgpu_atombios_crtc.c | 269 if (adev->mode_info.crtcs[i] &&
270 adev->mode_info.crtcs[i]->enabled &&
272 pll_id == adev->mode_info.crtcs[i]->pll_id) {
|
| amdgpu_dce_v10_0.c | 243 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
710 u32 num_heads; /* number of active crtcs */
1172 if (adev->mode_info.crtcs[i]->base.enabled)
1176 mode = &adev->mode_info.crtcs[i]->base.mode;
1177 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1178 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
2238 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2585 if (adev->mode_info.crtcs[i] &&
2586 adev->mode_info.crtcs[i]->enabled &&
2588 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id)
[all...] |
| amdgpu_dce_v11_0.c | 261 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
736 u32 num_heads; /* number of active crtcs */
1198 if (adev->mode_info.crtcs[i]->base.enabled)
1202 mode = &adev->mode_info.crtcs[i]->base.mode;
1203 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1204 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
2271 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2664 if (adev->mode_info.crtcs[i] &&
2665 adev->mode_info.crtcs[i]->enabled &&
2667 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id)
[all...] |
| amdgpu_dce_v8_0.c | 191 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
645 u32 num_heads; /* number of active crtcs */
1109 if (adev->mode_info.crtcs[i]->base.enabled)
1113 mode = &adev->mode_info.crtcs[i]->base.mode;
1114 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1115 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
2128 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2486 if (adev->mode_info.crtcs[i] &&
2487 adev->mode_info.crtcs[i]->enabled &&
2489 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id)
[all...] |
| amdgpu_mode.h | 321 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; member in struct:amdgpu_mode_info
350 int num_crtc; /* number of crtcs */
|
| amdgpu_display.c | 83 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
301 /* if we have active crtcs and we don't have a power ref,
307 /* if we have no active crtcs, then drop the power ref
870 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
|
| amdgpu_kms.c | 489 crtc = (struct drm_crtc *)minfo->crtcs[i];
1146 if (adev->mode_info.crtcs[pipe]) {
1159 &adev->mode_info.crtcs[pipe]->base.hwmode);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_display.h | 446 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
447 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
463 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
464 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
465 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
472 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
473 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
474 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_rs690.c | 258 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
261 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
604 if (rdev->mode_info.crtcs[0]->base.enabled)
605 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
606 if (rdev->mode_info.crtcs[1]->base.enabled)
607 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
631 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
632 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
634 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true);
635 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true)
[all...] |
| radeon_rv515.c | 1250 if (rdev->mode_info.crtcs[0]->base.enabled)
1251 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1252 if (rdev->mode_info.crtcs[1]->base.enabled)
1253 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1256 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
1257 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
1259 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false);
1260 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false);
1292 if (rdev->mode_info.crtcs[0]->base.enabled)
1293 mode0 = &rdev->mode_info.crtcs[0]->base.mode
[all...] |
| radeon_rs600.c | 125 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
156 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
328 /* disable any active CRTCs */
346 /* enable any active CRTCs */
942 if (rdev->mode_info.crtcs[0]->base.enabled)
943 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
944 if (rdev->mode_info.crtcs[1]->base.enabled)
945 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
|
| radeon_display.c | 291 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
347 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
372 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
419 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
651 /* if we have active crtcs and we don't have a power ref,
657 /* if we have no active crtcs, then drop the power ref
692 rdev->mode_info.crtcs[index] = radeon_crtc;
1618 /* allocate crtcs */
1947 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
|
| radeon_kms.c | 106 * (crtcs, encoders, hotplug detect, etc.).
266 crtc = (struct drm_crtc *)minfo->crtcs[i];
780 if (rdev->mode_info.crtcs[pipe]) {
793 &rdev->mode_info.crtcs[pipe]->base.hwmode);
|
| radeon_r100.c | 169 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
202 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
250 /* don't use the power state if crtcs are active and no display flag is set */
461 /* disable any active CRTCs */
492 /* enable any active CRTCs */
3249 if (rdev->mode_info.crtcs[0]->base.enabled) {
3251 rdev->mode_info.crtcs[0]->base.primary->fb;
3253 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3257 if (rdev->mode_info.crtcs[1]->base.enabled) {
3259 rdev->mode_info.crtcs[1]->base.primary->fb
[all...] |
| radeon_atombios_crtc.c | 471 if (rdev->mode_info.crtcs[i] &&
472 rdev->mode_info.crtcs[i]->enabled &&
474 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
1768 * crtcs/encoders.
1852 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2197 if (rdev->mode_info.crtcs[i] &&
2198 rdev->mode_info.crtcs[i]->enabled &&
2200 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/ |
| nouveau_dispnv50_disp.c | 2471 int crtcs, ret, i; local
2513 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2516 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2518 crtcs = 0x3;
2520 for (i = 0; i < fls(crtcs); i++) {
2523 if (!(crtcs & (1 << i)))
2550 head->msto->encoder.possible_crtcs = crtcs;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm_irq.c | 620 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];
|
