| /src/sys/arch/mips/rmi/ |
| rmixl_iobus.c | 70 uint32_t cs_mask; /* address mask on the Peripherals I/O Bus */ member in struct:__anon1689
177 cs->cs_mask = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
179 cs->cs_mask |= __BITS(15,0);
184 i, cs->cs_addr, cs->cs_mask, cs->cs_dev_parm);
273 if ((ia.ia_iobus_size - 1) > (bus_size_t)cs->cs_mask) {
276 ia.ia_iobus_size, ia.ia_cs, cs->cs_mask);
280 ia.ia_iobus_size = (bus_size_t)cs->cs_mask + 1;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_clock_source.h | 162 const struct dce110_clk_src_mask *cs_mask; member in struct:dce110_clk_src
189 const struct dce110_clk_src_mask *cs_mask);
198 const struct dce110_clk_src_mask *cs_mask);
207 const struct dce110_clk_src_mask *cs_mask);
|
| amdgpu_dce_clock_source.c | 57 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
836 if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE)
1320 const struct dce110_clk_src_mask *cs_mask)
1332 clk_src->cs_mask = cs_mask;
1345 clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1347 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV;
1364 clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1366 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV;
1420 const struct dce110_clk_src_mask *cs_mask)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| amdgpu_dce100_resource.c | 331 static const struct dce110_clk_src_mask cs_mask = { variable in typeref:struct:dce110_clk_src_mask
717 regs, &cs_shift, &cs_mask)) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| amdgpu_dce120_resource.c | 421 static const struct dce110_clk_src_mask cs_mask = { variable in typeref:struct:dce110_clk_src_mask
545 regs, &cs_shift, &cs_mask)) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_resource.c | 369 static const struct dce110_clk_src_mask cs_mask = { variable in typeref:struct:dce110_clk_src_mask
763 regs, &cs_shift, &cs_mask)) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_resource.c | 375 static const struct dce110_clk_src_mask cs_mask = { variable in typeref:struct:dce110_clk_src_mask
735 regs, &cs_shift, &cs_mask)) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| amdgpu_dce80_resource.c | 358 static const struct dce110_clk_src_mask cs_mask = { variable in typeref:struct:dce110_clk_src_mask
750 regs, &cs_shift, &cs_mask)) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_resource.c | 527 static const struct dce110_clk_src_mask cs_mask = { variable in typeref:struct:dce110_clk_src_mask
828 regs, &cs_shift, &cs_mask)) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 353 static const struct dce110_clk_src_mask cs_mask = { variable in typeref:struct:dce110_clk_src_mask
1203 regs, &cs_shift, &cs_mask)) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_resource.c | 448 static const struct dce110_clk_src_mask cs_mask = { variable in typeref:struct:dce110_clk_src_mask
1196 regs, &cs_shift, &cs_mask)) {
|
