1 /* $NetBSD: rmixl_iobus.c,v 1.7 2021/08/07 16:18:59 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2011 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Cliff Neighbors 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * RMI Peripherals IO Bus support 34 * - interface to NOR, NAND, PCMCIA Memory controllers, &etc. 35 * - manages the 10 Chip Selects 36 * - manages the "Flash" interrupts 37 * - manages the "Flash" errors 38 */ 39 40 /* 41 * iobus control registers are accessed as 32 bits. 42 * ALEn and CLEn NAND control registers are defined as 8 bits wide 43 * but that seems to be a documentation error. 44 * 45 * iobus data access may be as 1 or 2 or 4 bytes, even if device is 1 byte wide; 46 * the controller will sequence the bytes, in big-endian order. 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: rmixl_iobus.c,v 1.7 2021/08/07 16:18:59 thorpej Exp $"); 51 52 #include "locators.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/device.h> 57 58 #include <sys/bus.h> 59 60 #include <mips/rmi/rmixlreg.h> 61 #include <mips/rmi/rmixlvar.h> 62 #include <mips/rmi/rmixl_intr.h> 63 #include <mips/rmi/rmixl_obiovar.h> 64 #include <mips/rmi/rmixl_iobusvar.h> 65 // #include <mips/rmi/rmixl_gpiovar.h> 66 67 typedef struct { 68 bool cs_allocated; 69 uint32_t cs_addr; /* base address on the Peripherals I/O Bus */ 70 uint32_t cs_mask; /* address mask on the Peripherals I/O Bus */ 71 uint32_t cs_dev_parm; 72 } rmixl_iobus_csconfig_t; 73 74 typedef struct rmixl_iobus_softc { 75 device_t sc_dev; 76 bus_space_tag_t sc_obio_bst; /* for iobus device controller access */ 77 bus_space_handle_t sc_obio_bsh; /* " " " " " */ 78 bus_addr_t sc_obio_addr; 79 bus_size_t sc_obio_size; 80 bus_space_tag_t sc_iobus_bst; /* for iobus access */ 81 rmixl_iobus_csconfig_t sc_csconfig[RMIXL_FLASH_NCS]; 82 } rmixl_iobus_softc_t; 83 84 85 static int rmixl_iobus_match(device_t, cfdata_t, void *); 86 static void rmixl_iobus_attach(device_t, device_t, void *); 87 static void rmixl_iobus_csconfig_init(struct rmixl_iobus_softc *); 88 static int rmixl_iobus_print(void *, const char *); 89 static int rmixl_iobus_search(device_t, cfdata_t, const int *, void *); 90 #ifdef NOTYET 91 static int rmixl_iobus_intr(void *); 92 #endif 93 94 #ifdef RMIXL_IOBUS_DEBUG 95 rmixl_iobus_softc_t *rmixl_iobus_sc; 96 #endif 97 98 99 CFATTACH_DECL_NEW(rmixl_iobus, sizeof (rmixl_iobus_softc_t), 100 rmixl_iobus_match, rmixl_iobus_attach, NULL, NULL); 101 102 int 103 rmixl_iobus_match(device_t parent, cfdata_t match, void *aux) 104 { 105 struct obio_attach_args *obio = aux; 106 107 if (obio->obio_addr == RMIXL_IO_DEV_FLASH) 108 return rmixl_probe_4((volatile uint32_t *) 109 RMIXL_IOREG_VADDR(obio->obio_addr)); 110 111 return 0; 112 } 113 114 void 115 rmixl_iobus_attach(device_t parent, device_t self, void *aux) 116 { 117 rmixl_iobus_softc_t *sc = device_private(self); 118 struct obio_attach_args *obio = aux; 119 struct rmixl_config *rcp = &rmixl_configuration; 120 uint64_t r; 121 int err; 122 123 #ifdef RMIXL_IOBUS_DEBUG 124 rmixl_iobus_sc = sc; 125 #endif 126 sc->sc_dev = self; 127 sc->sc_obio_bst = obio->obio_eb_bst; 128 sc->sc_obio_addr = obio->obio_addr; 129 sc->sc_obio_size = 0x1000; 130 131 err = bus_space_map(sc->sc_obio_bst, sc->sc_obio_addr, 132 sc->sc_obio_size, 0, &sc->sc_obio_bsh); 133 if (err != 0) { 134 aprint_error_dev(self, 135 "bus space map err %d, iobus space\n", err); 136 return; 137 } 138 139 r = RMIXL_IOREG_READ(RMIXL_SBC_FLASH_BAR); 140 KASSERT((r & 1) != 0); /* BAR is enabled */ 141 rcp->rc_flash_pbase = RMIXL_FLASH_BAR_TO_BA(r); 142 rcp->rc_flash_mask = RMIXL_FLASH_BAR_TO_MASK(r); 143 144 aprint_normal("\n"); 145 aprint_debug_dev(self, 146 "Flash BAR pbase %#" PRIx64 " mask %#" PRIx64 "\n", 147 rcp->rc_flash_pbase, rcp->rc_flash_mask); 148 149 /* initialize iobus bus space */ 150 rmixl_iobus_bus_mem_init(&rcp->rc_iobus_memt, rcp); 151 sc->sc_iobus_bst = (bus_space_tag_t)&rcp->rc_iobus_memt; 152 153 /* disable all Flash interrupts */ 154 bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh, 155 RMIXL_FLASH_INT_MASK, 0); 156 157 /* write-1-to-clear Flash interrupt status */ 158 bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh, 159 RMIXL_FLASH_INT_STATUS, ~0); 160 161 rmixl_iobus_csconfig_init(sc); 162 163 /* attach any children */ 164 config_search(self, NULL, 165 CFARGS(.search = rmixl_iobus_search)); 166 } 167 168 static void 169 rmixl_iobus_csconfig_init(struct rmixl_iobus_softc *sc) 170 { 171 rmixl_iobus_csconfig_t *cs = &sc->sc_csconfig[0]; 172 173 for (int i=0; i < RMIXL_FLASH_NCS; i++) { 174 memset(cs, 0, sizeof(rmixl_iobus_csconfig_t)); 175 cs->cs_addr = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh, 176 RMIXL_FLASH_CSBASE_ADDRn(i)) << 16; 177 cs->cs_mask = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh, 178 RMIXL_FLASH_CSADDR_MASKn(i)) << 16; 179 cs->cs_mask |= __BITS(15,0); 180 cs->cs_dev_parm = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh, 181 RMIXL_FLASH_CSDEV_PARMn(i)); 182 aprint_debug_dev(sc->sc_dev, 183 "CS#%d: addr 0x%08x mask 0x%08x parm 0x%08x\n", 184 i, cs->cs_addr, cs->cs_mask, cs->cs_dev_parm); 185 cs++; 186 } 187 } 188 189 190 static int 191 rmixl_iobus_print(void *aux, const char *pnp) 192 { 193 struct rmixl_iobus_attach_args *ia = aux; 194 195 if (ia->ia_cs != RMIXL_IOBUSCF_CS_DEFAULT) 196 aprint_normal(" CS#%d", ia->ia_cs); 197 if (ia->ia_iobus_addr != RMIXL_IOBUSCF_ADDR_DEFAULT) { 198 aprint_normal(" addr %#" PRIxBUSADDR, ia->ia_iobus_addr); 199 if (ia->ia_iobus_size != RMIXL_IOBUSCF_SIZE_DEFAULT) 200 aprint_normal("-%#" PRIxBUSSIZE, 201 ia->ia_iobus_addr + (ia->ia_iobus_size - 1)); 202 } 203 if (ia->ia_iobus_intr != RMIXL_IOBUSCF_INTR_DEFAULT) 204 aprint_normal(" intr %d", ia->ia_iobus_intr); 205 206 return UNCONF; 207 } 208 209 static int 210 rmixl_iobus_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 211 { 212 struct rmixl_iobus_softc *sc = device_private(parent); 213 struct rmixl_iobus_attach_args ia; 214 rmixl_iobus_csconfig_t *cs; 215 216 ia.ia_obio_bst = sc->sc_obio_bst; 217 ia.ia_obio_bsh = sc->sc_obio_bsh; 218 ia.ia_iobus_bst = sc->sc_iobus_bst; 219 ia.ia_iobus_addr = (bus_addr_t)cf->cf_loc[RMIXL_IOBUSCF_ADDR]; 220 ia.ia_iobus_size = (bus_size_t)cf->cf_loc[RMIXL_IOBUSCF_SIZE]; 221 ia.ia_iobus_intr = cf->cf_loc[RMIXL_IOBUSCF_INTR]; 222 ia.ia_cs = cf->cf_loc[RMIXL_IOBUSCF_CS]; 223 224 if (ia.ia_cs != RMIXL_IOBUSCF_CS_DEFAULT) { 225 /* CS is configured */ 226 cs = &sc->sc_csconfig[ia.ia_cs]; 227 228 /* ensure exclusive use of chip select */ 229 if (cs->cs_allocated) { 230 aprint_error_dev(parent, "CS#%d already allocated\n", 231 ia.ia_cs); 232 return 0; 233 } 234 if (ia.ia_iobus_addr != RMIXL_IOBUSCF_ADDR_DEFAULT) { 235 if (ia.ia_iobus_addr != cs->cs_addr) { 236 /* 237 * both CS and addr are configured, 238 * ensure they match 239 */ 240 aprint_error_dev(parent, 241 "CS#%d addr 0x%08x mismatch cf_loc " 242 "addr 0x%08" PRIxBUSADDR "\n", 243 ia.ia_cs, cs->cs_addr, ia.ia_iobus_addr); 244 return 0; 245 } 246 } else { 247 /* no addr configured, pull from CS */ 248 ia.ia_iobus_addr = cs->cs_addr; 249 } 250 } else { 251 /* addr is configured, CS is not; search for matching CS */ 252 bool found = false; 253 cs = &sc->sc_csconfig[0]; 254 for (int i=0; i < RMIXL_FLASH_NCS; i++) { 255 if (cs->cs_allocated) 256 continue; 257 if (cs->cs_addr == ia.ia_iobus_addr) { 258 ia.ia_cs = i; 259 found = true; 260 break; 261 } 262 cs++; 263 } 264 if (! found) { 265 aprint_error_dev(parent, "no CS for addr 0x%08" 266 PRIxBUSADDR "\n", ia.ia_iobus_addr); 267 return 0; 268 } 269 } 270 271 if (ia.ia_iobus_size != RMIXL_IOBUSCF_SIZE_DEFAULT) { 272 /* ensure size fits w/ CS mask */ 273 if ((ia.ia_iobus_size - 1) > (bus_size_t)cs->cs_mask) { 274 aprint_error_dev(parent, "size %#" PRIxBUSSIZE 275 " exceeds CS#%d mask 0x%08x\n", 276 ia.ia_iobus_size, ia.ia_cs, cs->cs_mask); 277 } 278 } else { 279 /* size not configured, pull from CS */ 280 ia.ia_iobus_size = (bus_size_t)cs->cs_mask + 1; 281 } 282 283 ia.ia_dev_parm = cs->cs_dev_parm; 284 285 if (config_probe(parent, cf, &ia)) { 286 cs->cs_allocated = true; 287 config_attach(parent, cf, &ia, rmixl_iobus_print, CFARGS_NONE); 288 } 289 290 return 0; 291 } 292 293 294 #ifdef NOTYET 295 296 void 297 rmixl_iobus_intr_disestablish(void *uh, void *ih) 298 { 299 rmixl_iobus_softc_t *sc = uh; 300 u_int intr; 301 302 for (intr=0; intr <= RMIXL_UB_INTERRUPT_MAX; intr++) { 303 if (ih == &sc->sc_dispatch[intr]) { 304 uint32_t r; 305 306 /* disable this interrupt in the usb interface */ 307 r = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh, 308 RMIXL_USB_INTERRUPT_ENABLE); 309 r &= 1 << intr; 310 bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh, 311 RMIXL_USB_INTERRUPT_ENABLE, r); 312 313 /* free the dispatch slot */ 314 sc->sc_dispatch[intr].func = NULL; 315 sc->sc_dispatch[intr].arg = NULL; 316 317 break; 318 } 319 } 320 } 321 322 void * 323 rmixl_iobus_intr_establish(void *uh, u_int intr, int (func)(void *), void *arg) 324 { 325 rmixl_iobus_softc_t *sc = uh; 326 uint32_t r; 327 void *ih = NULL; 328 int s; 329 330 s = splusb(); 331 332 if (intr > RMIXL_UB_INTERRUPT_MAX) { 333 aprint_error_dev(sc->sc_dev, "invalid intr %d\n", intr); 334 goto out; 335 } 336 337 if (sc->sc_dispatch[intr].func != NULL) { 338 aprint_error_dev(sc->sc_dev, "intr %dq busy\n", intr); 339 goto out; 340 } 341 342 sc->sc_dispatch[intr].func = func; 343 sc->sc_dispatch[intr].arg = arg; 344 ih = &sc->sc_dispatch[intr]; 345 346 /* enable this interrupt in the usb interface */ 347 r = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh, 348 RMIXL_USB_INTERRUPT_ENABLE); 349 r |= 1 << intr; 350 bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh, 351 RMIXL_USB_INTERRUPT_ENABLE, r); 352 353 out: 354 splx(s); 355 return ih; 356 } 357 358 static int 359 rmixl_iobus_intr(void *arg) 360 { 361 rmixl_iobus_softc_t *sc = arg; 362 uint32_t r; 363 int intr; 364 int rv = 0; 365 366 r = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh, 367 RMIXL_USB_INTERRUPT_STATUS); 368 if (r != 0) { 369 for (intr=0; intr <= RMIXL_UB_INTERRUPT_MAX; intr++) { 370 uint32_t bit = 1 << intr; 371 if ((r & bit) != 0) { 372 int (*f)(void *) = sc->sc_dispatch[intr].func; 373 void *a = sc->sc_dispatch[intr].arg; 374 if (f != NULL) { 375 (void)(*f)(a); 376 sc->sc_dispatch[intr].count.ev_count++; 377 rv = 1; 378 } 379 } 380 } 381 } 382 383 return rv; 384 } 385 386 #endif /* NOTYET */ 387
Indexes created Sat Sep 20 22:09:52 GMT 2025