| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_bios.c | 324 u32 d1vga_control; local
331 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
341 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
356 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
368 uint32_t d1vga_control; local
378 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
389 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
426 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
437 uint32_t d1vga_control; local
451 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL)
515 uint32_t d1vga_control; local
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_vi.c | 385 u32 d1vga_control = 0; local
393 d1vga_control = RREG32(mmD1VGA_CONTROL);
404 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
419 WREG32(mmD1VGA_CONTROL, d1vga_control);
|
| amdgpu_gmc_v9_0.c | 1035 u32 d1vga_control; local
1045 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1046 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
|
| amdgpu_gmc_v10_0.c | 743 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); local
746 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
|
| amdgpu_gmc_v6_0.c | 824 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); local
827 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
|
| amdgpu_cik.c | 901 u32 d1vga_control = 0; local
909 d1vga_control = RREG32(mmD1VGA_CONTROL);
920 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
935 WREG32(mmD1VGA_CONTROL, d1vga_control);
|
| amdgpu_si.c | 1132 u32 d1vga_control = 0; local
1140 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
1151 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
1166 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
|
| amdgpu_gmc_v7_0.c | 982 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); local
985 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
|
| amdgpu_gmc_v8_0.c | 1094 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); local
1097 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
|
