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    Searched refs:dclk (Results 1 - 25 of 69) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_bw.c 19 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; member in struct:intel_qgv_point
109 sp->dclk = val & 0xffff;
140 DRM_DEBUG_KMS("QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n",
141 i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras,
148 static int icl_calc_bw(int dclk, int num, int den)
151 return DIV_ROUND_CLOSEST(num * dclk * 100, den * 6);
156 u16 dclk = 0; local in function:icl_sagv_max_dclk
160 dclk = max(dclk, qi->points[i].dclk);
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
hwmgr_ppt.h 61 uint32_t dclk; /* UVD D-clock */ member in struct:phm_ppt_v1_mm_clock_voltage_dependency_record
smu10_hwmgr.h 100 uint32_t dclk; member in struct:smu10_uvd_clocks
smu7_hwmgr.h 71 uint32_t dclk; member in struct:smu7_uvd_clocks
smu8_hwmgr.h 117 uint32_t dclk; member in struct:smu8_uvd_clocks
amdgpu_smu8_hwmgr.c 530 (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
1394 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
1697 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; local in function:smu8_read_sensor
1743 dclk = uvd_table->entries[uvd_index].dclk;
1744 *((uint32_t *)value) = dclk;
vega10_hwmgr.h 99 uint32_t dclk; member in struct:vega10_uvd_clocks
vega20_hwmgr.h 116 uint32_t dclk; member in struct:vega20_uvd_clocks
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
power_state.h 146 uint32_t DCLK;
186 unsigned long dclk; member in struct:pp_clock_engine_request
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rs780_dpm.c 577 (new_ps->dclk == old_ps->dclk))
583 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
594 (new_ps->dclk == old_ps->dclk))
600 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
734 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
737 rps->dclk = 0;
741 if ((rps->vclk == 0) || (rps->dclk == 0)) {
743 rps->dclk = RS780_DEFAULT_DCLK_FREQ
    [all...]
trinity_dpm.h 72 u32 dclk; member in struct:trinity_uvd_clock_table_entry
radeon_rv770_dpm.c 1444 (new_ps->dclk == old_ps->dclk))
1450 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1461 (new_ps->dclk == old_ps->dclk))
1467 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
2159 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2162 rps->dclk = 0;
2166 if ((rps->vclk == 0) || (rps->dclk == 0)) {
2168 rps->dclk = RV770_DEFAULT_DCLK_FREQ
    [all...]
radeon_trinity_dpm.c 903 if ((rps->vclk == 0) && (rps->dclk == 0))
916 (rps1->dclk == rps2->dclk) &&
948 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
959 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
1464 (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk))
1698 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1701 rps->dclk = 0;
1941 pi->sys_info.uvd_clock_table_entries[i].dclk
    [all...]
radeon_uvd.c 951 * @dclk: wanted DCLK
961 * @optimal_dclk_div: resulting dclk post divider
967 unsigned vclk, unsigned dclk,
982 vco_min = max(max(vco_min, vclk), dclk);
1002 /* calc dclk divider with current vco freq */
1003 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
1009 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
radeon_rv6xx_dpm.c 1524 (new_ps->dclk == old_ps->dclk))
1530 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1541 (new_ps->dclk == old_ps->dclk))
1547 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1809 rps->dclk = RV6XX_DEFAULT_DCLK_FREQ;
1812 rps->dclk = 0;
2020 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
    [all...]
radeon_sumo_dpm.c 829 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
846 (new_rps->dclk == old_rps->dclk))
864 (new_rps->dclk == old_rps->dclk))
1420 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1423 rps->dclk = 0;
1807 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1831 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk)
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radeon_asic.h 413 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
480 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
537 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
538 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
751 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
789 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
radeon_ni_dpm.c 3520 (new_ps->dclk == old_ps->dclk))
3527 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
3538 (new_ps->dclk == old_ps->dclk))
3545 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
3909 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
3912 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
3915 rps->dclk = 0;
4295 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk)
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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dm_services_types.h 68 struct dm_pp_clock_range dclk; member in struct:dm_pp_gpu_clock_range
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dpm.h 63 u32 dclk; member in struct:amdgpu_ps
165 u32 dclk; member in struct:amdgpu_uvd_clock_voltage_dependency_entry
amdgpu_vi.c 836 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
845 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
853 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
amdgpu_kv_dpm.c 925 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
931 (u8)kv_get_clk_bypass(adev, table->entries[i].dclk);
940 table->entries[i].dclk, false, &dividers);
2294 pi->video_start = new_rps->dclk || new_rps->vclk ||
2671 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2674 rps->dclk = 0;
2909 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
3282 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
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  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
rk3188.dtsi 123 reset-names = "axi", "ahb", "dclk";
140 reset-names = "axi", "ahb", "dclk";
365 lcdc1_dclk: lcdc1-dclk {
imx6dl-eckelmann-ci4x10.dts 50 dclk-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
220 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */
rk3066a.dtsi 77 reset-names = "axi", "ahb", "dclk";
103 reset-names = "axi", "ahb", "dclk";

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