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      1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2 /*
      3  * Copyright (c) 2013 MundoReader S.L.
      4  * Author: Heiko Stuebner <heiko (a] sntech.de>
      5  */
      6 
      7 #include <dt-bindings/gpio/gpio.h>
      8 #include <dt-bindings/pinctrl/rockchip.h>
      9 #include <dt-bindings/clock/rk3188-cru.h>
     10 #include <dt-bindings/power/rk3188-power.h>
     11 #include "rk3xxx.dtsi"
     12 
     13 / {
     14 	compatible = "rockchip,rk3188";
     15 
     16 	cpus {
     17 		#address-cells = <1>;
     18 		#size-cells = <0>;
     19 		enable-method = "rockchip,rk3066-smp";
     20 
     21 		cpu0: cpu@0 {
     22 			device_type = "cpu";
     23 			compatible = "arm,cortex-a9";
     24 			next-level-cache = <&L2>;
     25 			reg = <0x0>;
     26 			clock-latency = <40000>;
     27 			clocks = <&cru ARMCLK>;
     28 			operating-points-v2 = <&cpu0_opp_table>;
     29 			resets = <&cru SRST_CORE0>;
     30 		};
     31 		cpu1: cpu@1 {
     32 			device_type = "cpu";
     33 			compatible = "arm,cortex-a9";
     34 			next-level-cache = <&L2>;
     35 			reg = <0x1>;
     36 			operating-points-v2 = <&cpu0_opp_table>;
     37 			resets = <&cru SRST_CORE1>;
     38 		};
     39 		cpu2: cpu@2 {
     40 			device_type = "cpu";
     41 			compatible = "arm,cortex-a9";
     42 			next-level-cache = <&L2>;
     43 			reg = <0x2>;
     44 			operating-points-v2 = <&cpu0_opp_table>;
     45 			resets = <&cru SRST_CORE2>;
     46 		};
     47 		cpu3: cpu@3 {
     48 			device_type = "cpu";
     49 			compatible = "arm,cortex-a9";
     50 			next-level-cache = <&L2>;
     51 			reg = <0x3>;
     52 			operating-points-v2 = <&cpu0_opp_table>;
     53 			resets = <&cru SRST_CORE3>;
     54 		};
     55 	};
     56 
     57 	cpu0_opp_table: opp_table0 {
     58 		compatible = "operating-points-v2";
     59 		opp-shared;
     60 
     61 		opp-312000000 {
     62 			opp-hz = /bits/ 64 <312000000>;
     63 			opp-microvolt = <875000>;
     64 			clock-latency-ns = <40000>;
     65 		};
     66 		opp-504000000 {
     67 			opp-hz = /bits/ 64 <504000000>;
     68 			opp-microvolt = <925000>;
     69 		};
     70 		opp-600000000 {
     71 			opp-hz = /bits/ 64 <600000000>;
     72 			opp-microvolt = <950000>;
     73 			opp-suspend;
     74 		};
     75 		opp-816000000 {
     76 			opp-hz = /bits/ 64 <816000000>;
     77 			opp-microvolt = <975000>;
     78 		};
     79 		opp-1008000000 {
     80 			opp-hz = /bits/ 64 <1008000000>;
     81 			opp-microvolt = <1075000>;
     82 		};
     83 		opp-1200000000 {
     84 			opp-hz = /bits/ 64 <1200000000>;
     85 			opp-microvolt = <1150000>;
     86 		};
     87 		opp-1416000000 {
     88 			opp-hz = /bits/ 64 <1416000000>;
     89 			opp-microvolt = <1250000>;
     90 		};
     91 		opp-1608000000 {
     92 			opp-hz = /bits/ 64 <1608000000>;
     93 			opp-microvolt = <1350000>;
     94 		};
     95 	};
     96 
     97 	display-subsystem {
     98 		compatible = "rockchip,display-subsystem";
     99 		ports = <&vop0_out>, <&vop1_out>;
    100 	};
    101 
    102 	sram: sram@10080000 {
    103 		compatible = "mmio-sram";
    104 		reg = <0x10080000 0x8000>;
    105 		#address-cells = <1>;
    106 		#size-cells = <1>;
    107 		ranges = <0 0x10080000 0x8000>;
    108 
    109 		smp-sram@0 {
    110 			compatible = "rockchip,rk3066-smp-sram";
    111 			reg = <0x0 0x50>;
    112 		};
    113 	};
    114 
    115 	vop0: vop@1010c000 {
    116 		compatible = "rockchip,rk3188-vop";
    117 		reg = <0x1010c000 0x1000>;
    118 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
    119 		clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
    120 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
    121 		power-domains = <&power RK3188_PD_VIO>;
    122 		resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
    123 		reset-names = "axi", "ahb", "dclk";
    124 		status = "disabled";
    125 
    126 		vop0_out: port {
    127 			#address-cells = <1>;
    128 			#size-cells = <0>;
    129 		};
    130 	};
    131 
    132 	vop1: vop@1010e000 {
    133 		compatible = "rockchip,rk3188-vop";
    134 		reg = <0x1010e000 0x1000>;
    135 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
    136 		clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
    137 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
    138 		power-domains = <&power RK3188_PD_VIO>;
    139 		resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
    140 		reset-names = "axi", "ahb", "dclk";
    141 		status = "disabled";
    142 
    143 		vop1_out: port {
    144 			#address-cells = <1>;
    145 			#size-cells = <0>;
    146 		};
    147 	};
    148 
    149 	timer3: timer@2000e000 {
    150 		compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
    151 		reg = <0x2000e000 0x20>;
    152 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
    153 		clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>;
    154 		clock-names = "pclk", "timer";
    155 	};
    156 
    157 	timer6: timer@200380a0 {
    158 		compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
    159 		reg = <0x200380a0 0x20>;
    160 		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
    161 		clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>;
    162 		clock-names = "pclk", "timer";
    163 	};
    164 
    165 	i2s0: i2s@1011a000 {
    166 		compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
    167 		reg = <0x1011a000 0x2000>;
    168 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
    169 		pinctrl-names = "default";
    170 		pinctrl-0 = <&i2s0_bus>;
    171 		clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
    172 		clock-names = "i2s_clk", "i2s_hclk";
    173 		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
    174 		dma-names = "tx", "rx";
    175 		rockchip,playback-channels = <2>;
    176 		rockchip,capture-channels = <2>;
    177 		#sound-dai-cells = <0>;
    178 		status = "disabled";
    179 	};
    180 
    181 	spdif: sound@1011e000 {
    182 		compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
    183 		reg = <0x1011e000 0x2000>;
    184 		#sound-dai-cells = <0>;
    185 		clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
    186 		clock-names = "mclk", "hclk";
    187 		dmas = <&dmac1_s 8>;
    188 		dma-names = "tx";
    189 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
    190 		pinctrl-names = "default";
    191 		pinctrl-0 = <&spdif_tx>;
    192 		status = "disabled";
    193 	};
    194 
    195 	cru: clock-controller@20000000 {
    196 		compatible = "rockchip,rk3188-cru";
    197 		reg = <0x20000000 0x1000>;
    198 		rockchip,grf = <&grf>;
    199 
    200 		#clock-cells = <1>;
    201 		#reset-cells = <1>;
    202 	};
    203 
    204 	efuse: efuse@20010000 {
    205 		compatible = "rockchip,rk3188-efuse";
    206 		reg = <0x20010000 0x4000>;
    207 		#address-cells = <1>;
    208 		#size-cells = <1>;
    209 		clocks = <&cru PCLK_EFUSE>;
    210 		clock-names = "pclk_efuse";
    211 
    212 		cpu_leakage: cpu_leakage@17 {
    213 			reg = <0x17 0x1>;
    214 		};
    215 	};
    216 
    217 	pinctrl: pinctrl {
    218 		compatible = "rockchip,rk3188-pinctrl";
    219 		rockchip,grf = <&grf>;
    220 		rockchip,pmu = <&pmu>;
    221 
    222 		#address-cells = <1>;
    223 		#size-cells = <1>;
    224 		ranges;
    225 
    226 		gpio0: gpio0@2000a000 {
    227 			compatible = "rockchip,rk3188-gpio-bank0";
    228 			reg = <0x2000a000 0x100>;
    229 			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
    230 			clocks = <&cru PCLK_GPIO0>;
    231 
    232 			gpio-controller;
    233 			#gpio-cells = <2>;
    234 
    235 			interrupt-controller;
    236 			#interrupt-cells = <2>;
    237 		};
    238 
    239 		gpio1: gpio1@2003c000 {
    240 			compatible = "rockchip,gpio-bank";
    241 			reg = <0x2003c000 0x100>;
    242 			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
    243 			clocks = <&cru PCLK_GPIO1>;
    244 
    245 			gpio-controller;
    246 			#gpio-cells = <2>;
    247 
    248 			interrupt-controller;
    249 			#interrupt-cells = <2>;
    250 		};
    251 
    252 		gpio2: gpio2@2003e000 {
    253 			compatible = "rockchip,gpio-bank";
    254 			reg = <0x2003e000 0x100>;
    255 			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
    256 			clocks = <&cru PCLK_GPIO2>;
    257 
    258 			gpio-controller;
    259 			#gpio-cells = <2>;
    260 
    261 			interrupt-controller;
    262 			#interrupt-cells = <2>;
    263 		};
    264 
    265 		gpio3: gpio3@20080000 {
    266 			compatible = "rockchip,gpio-bank";
    267 			reg = <0x20080000 0x100>;
    268 			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
    269 			clocks = <&cru PCLK_GPIO3>;
    270 
    271 			gpio-controller;
    272 			#gpio-cells = <2>;
    273 
    274 			interrupt-controller;
    275 			#interrupt-cells = <2>;
    276 		};
    277 
    278 		pcfg_pull_up: pcfg-pull-up {
    279 			bias-pull-up;
    280 		};
    281 
    282 		pcfg_pull_down: pcfg-pull-down {
    283 			bias-pull-down;
    284 		};
    285 
    286 		pcfg_pull_none: pcfg-pull-none {
    287 			bias-disable;
    288 		};
    289 
    290 		emmc {
    291 			emmc_clk: emmc-clk {
    292 				rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
    293 			};
    294 
    295 			emmc_cmd: emmc-cmd {
    296 				rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>;
    297 			};
    298 
    299 			emmc_rst: emmc-rst {
    300 				rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>;
    301 			};
    302 
    303 			/*
    304 			 * The data pins are shared between nandc and emmc and
    305 			 * not accessible through pinctrl. Also they should've
    306 			 * been already set correctly by firmware, as
    307 			 * flash/emmc is the boot-device.
    308 			 */
    309 		};
    310 
    311 		emac {
    312 			emac_xfer: emac-xfer {
    313 				rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */
    314 						<3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */
    315 						<3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */
    316 						<3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */
    317 						<3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */
    318 						<3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */
    319 						<3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */
    320 						<3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */
    321 			};
    322 
    323 			emac_mdio: emac-mdio {
    324 				rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
    325 						<3 RK_PD1 2 &pcfg_pull_none>;
    326 			};
    327 		};
    328 
    329 		i2c0 {
    330 			i2c0_xfer: i2c0-xfer {
    331 				rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
    332 						<1 RK_PD1 1 &pcfg_pull_none>;
    333 			};
    334 		};
    335 
    336 		i2c1 {
    337 			i2c1_xfer: i2c1-xfer {
    338 				rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>,
    339 						<1 RK_PD3 1 &pcfg_pull_none>;
    340 			};
    341 		};
    342 
    343 		i2c2 {
    344 			i2c2_xfer: i2c2-xfer {
    345 				rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>,
    346 						<1 RK_PD5 1 &pcfg_pull_none>;
    347 			};
    348 		};
    349 
    350 		i2c3 {
    351 			i2c3_xfer: i2c3-xfer {
    352 				rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>,
    353 						<3 RK_PB7 2 &pcfg_pull_none>;
    354 			};
    355 		};
    356 
    357 		i2c4 {
    358 			i2c4_xfer: i2c4-xfer {
    359 				rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>,
    360 						<1 RK_PD7 1 &pcfg_pull_none>;
    361 			};
    362 		};
    363 
    364 		lcdc1 {
    365 			lcdc1_dclk: lcdc1-dclk {
    366 				rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>;
    367 			};
    368 
    369 			lcdc1_den: lcdc1-den {
    370 				rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>;
    371 			};
    372 
    373 			lcdc1_hsync: lcdc1-hsync {
    374 				rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
    375 			};
    376 
    377 			lcdc1_vsync: lcdc1-vsync {
    378 				rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
    379 			};
    380 
    381 			lcdc1_rgb24: ldcd1-rgb24 {
    382 				rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
    383 						<2 RK_PA1 1 &pcfg_pull_none>,
    384 						<2 RK_PA2 1 &pcfg_pull_none>,
    385 						<2 RK_PA3 1 &pcfg_pull_none>,
    386 						<2 RK_PA4 1 &pcfg_pull_none>,
    387 						<2 RK_PA5 1 &pcfg_pull_none>,
    388 						<2 RK_PA6 1 &pcfg_pull_none>,
    389 						<2 RK_PA7 1 &pcfg_pull_none>,
    390 						<2 RK_PB0 1 &pcfg_pull_none>,
    391 						<2 RK_PB1 1 &pcfg_pull_none>,
    392 						<2 RK_PB2 1 &pcfg_pull_none>,
    393 						<2 RK_PB3 1 &pcfg_pull_none>,
    394 						<2 RK_PB4 1 &pcfg_pull_none>,
    395 						<2 RK_PB5 1 &pcfg_pull_none>,
    396 						<2 RK_PB6 1 &pcfg_pull_none>,
    397 						<2 RK_PB7 1 &pcfg_pull_none>,
    398 						<2 RK_PC0 1 &pcfg_pull_none>,
    399 						<2 RK_PC1 1 &pcfg_pull_none>,
    400 						<2 RK_PC2 1 &pcfg_pull_none>,
    401 						<2 RK_PC3 1 &pcfg_pull_none>,
    402 						<2 RK_PC4 1 &pcfg_pull_none>,
    403 						<2 RK_PC5 1 &pcfg_pull_none>,
    404 						<2 RK_PC6 1 &pcfg_pull_none>,
    405 						<2 RK_PC7 1 &pcfg_pull_none>;
    406 			};
    407 		};
    408 
    409 		pwm0 {
    410 			pwm0_out: pwm0-out {
    411 				rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
    412 			};
    413 		};
    414 
    415 		pwm1 {
    416 			pwm1_out: pwm1-out {
    417 				rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>;
    418 			};
    419 		};
    420 
    421 		pwm2 {
    422 			pwm2_out: pwm2-out {
    423 				rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>;
    424 			};
    425 		};
    426 
    427 		pwm3 {
    428 			pwm3_out: pwm3-out {
    429 				rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>;
    430 			};
    431 		};
    432 
    433 		spi0 {
    434 			spi0_clk: spi0-clk {
    435 				rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>;
    436 			};
    437 			spi0_cs0: spi0-cs0 {
    438 				rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>;
    439 			};
    440 			spi0_tx: spi0-tx {
    441 				rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>;
    442 			};
    443 			spi0_rx: spi0-rx {
    444 				rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>;
    445 			};
    446 			spi0_cs1: spi0-cs1 {
    447 				rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>;
    448 			};
    449 		};
    450 
    451 		spi1 {
    452 			spi1_clk: spi1-clk {
    453 				rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>;
    454 			};
    455 			spi1_cs0: spi1-cs0 {
    456 				rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>;
    457 			};
    458 			spi1_rx: spi1-rx {
    459 				rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>;
    460 			};
    461 			spi1_tx: spi1-tx {
    462 				rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>;
    463 			};
    464 			spi1_cs1: spi1-cs1 {
    465 				rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
    466 			};
    467 		};
    468 
    469 		uart0 {
    470 			uart0_xfer: uart0-xfer {
    471 				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>,
    472 						<1 RK_PA1 1 &pcfg_pull_none>;
    473 			};
    474 
    475 			uart0_cts: uart0-cts {
    476 				rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>;
    477 			};
    478 
    479 			uart0_rts: uart0-rts {
    480 				rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>;
    481 			};
    482 		};
    483 
    484 		uart1 {
    485 			uart1_xfer: uart1-xfer {
    486 				rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>,
    487 						<1 RK_PA5 1 &pcfg_pull_none>;
    488 			};
    489 
    490 			uart1_cts: uart1-cts {
    491 				rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
    492 			};
    493 
    494 			uart1_rts: uart1-rts {
    495 				rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>;
    496 			};
    497 		};
    498 
    499 		uart2 {
    500 			uart2_xfer: uart2-xfer {
    501 				rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>,
    502 						<1 RK_PB1 1 &pcfg_pull_none>;
    503 			};
    504 			/* no rts / cts for uart2 */
    505 		};
    506 
    507 		uart3 {
    508 			uart3_xfer: uart3-xfer {
    509 				rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>,
    510 						<1 RK_PB3 1 &pcfg_pull_none>;
    511 			};
    512 
    513 			uart3_cts: uart3-cts {
    514 				rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>;
    515 			};
    516 
    517 			uart3_rts: uart3-rts {
    518 				rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>;
    519 			};
    520 		};
    521 
    522 		sd0 {
    523 			sd0_clk: sd0-clk {
    524 				rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>;
    525 			};
    526 
    527 			sd0_cmd: sd0-cmd {
    528 				rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
    529 			};
    530 
    531 			sd0_cd: sd0-cd {
    532 				rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>;
    533 			};
    534 
    535 			sd0_wp: sd0-wp {
    536 				rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>;
    537 			};
    538 
    539 			sd0_pwr: sd0-pwr {
    540 				rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
    541 			};
    542 
    543 			sd0_bus1: sd0-bus-width1 {
    544 				rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
    545 			};
    546 
    547 			sd0_bus4: sd0-bus-width4 {
    548 				rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
    549 						<3 RK_PA5 1 &pcfg_pull_none>,
    550 						<3 RK_PA6 1 &pcfg_pull_none>,
    551 						<3 RK_PA7 1 &pcfg_pull_none>;
    552 			};
    553 		};
    554 
    555 		sd1 {
    556 			sd1_clk: sd1-clk {
    557 				rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
    558 			};
    559 
    560 			sd1_cmd: sd1-cmd {
    561 				rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>;
    562 			};
    563 
    564 			sd1_cd: sd1-cd {
    565 				rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>;
    566 			};
    567 
    568 			sd1_wp: sd1-wp {
    569 				rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>;
    570 			};
    571 
    572 			sd1_bus1: sd1-bus-width1 {
    573 				rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>;
    574 			};
    575 
    576 			sd1_bus4: sd1-bus-width4 {
    577 				rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>,
    578 						<3 RK_PC2 1 &pcfg_pull_none>,
    579 						<3 RK_PC3 1 &pcfg_pull_none>,
    580 						<3 RK_PC4 1 &pcfg_pull_none>;
    581 			};
    582 		};
    583 
    584 		i2s0 {
    585 			i2s0_bus: i2s0-bus {
    586 				rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
    587 						<1 RK_PC1 1 &pcfg_pull_none>,
    588 						<1 RK_PC2 1 &pcfg_pull_none>,
    589 						<1 RK_PC3 1 &pcfg_pull_none>,
    590 						<1 RK_PC4 1 &pcfg_pull_none>,
    591 						<1 RK_PC5 1 &pcfg_pull_none>;
    592 			};
    593 		};
    594 
    595 		spdif {
    596 			spdif_tx: spdif-tx {
    597 				rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>;
    598 			};
    599 		};
    600 	};
    601 };
    602 
    603 &emac {
    604 	compatible = "rockchip,rk3188-emac";
    605 };
    606 
    607 &global_timer {
    608 	interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
    609 	status = "disabled";
    610 };
    611 
    612 &local_timer {
    613 	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
    614 };
    615 
    616 &gpu {
    617 	compatible = "rockchip,rk3188-mali", "arm,mali-400";
    618 	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
    619 		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
    620 		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
    621 		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
    622 		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
    623 		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
    624 		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
    625 		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
    626 		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
    627 		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
    628 	interrupt-names = "gp",
    629 			  "gpmmu",
    630 			  "pp0",
    631 			  "ppmmu0",
    632 			  "pp1",
    633 			  "ppmmu1",
    634 			  "pp2",
    635 			  "ppmmu2",
    636 			  "pp3",
    637 			  "ppmmu3";
    638 	power-domains = <&power RK3188_PD_GPU>;
    639 };
    640 
    641 &grf {
    642 	compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
    643 
    644 	io_domains: io-domains {
    645 		compatible = "rockchip,rk3188-io-voltage-domain";
    646 		status = "disabled";
    647 	};
    648 
    649 	usbphy: usbphy {
    650 		compatible = "rockchip,rk3188-usb-phy",
    651 			     "rockchip,rk3288-usb-phy";
    652 		#address-cells = <1>;
    653 		#size-cells = <0>;
    654 		status = "disabled";
    655 
    656 		usbphy0: usb-phy@10c {
    657 			reg = <0x10c>;
    658 			clocks = <&cru SCLK_OTGPHY0>;
    659 			clock-names = "phyclk";
    660 			#clock-cells = <0>;
    661 			#phy-cells = <0>;
    662 		};
    663 
    664 		usbphy1: usb-phy@11c {
    665 			reg = <0x11c>;
    666 			clocks = <&cru SCLK_OTGPHY1>;
    667 			clock-names = "phyclk";
    668 			#clock-cells = <0>;
    669 			#phy-cells = <0>;
    670 		};
    671 	};
    672 };
    673 
    674 &i2c0 {
    675 	compatible = "rockchip,rk3188-i2c";
    676 	pinctrl-names = "default";
    677 	pinctrl-0 = <&i2c0_xfer>;
    678 };
    679 
    680 &i2c1 {
    681 	compatible = "rockchip,rk3188-i2c";
    682 	pinctrl-names = "default";
    683 	pinctrl-0 = <&i2c1_xfer>;
    684 };
    685 
    686 &i2c2 {
    687 	compatible = "rockchip,rk3188-i2c";
    688 	pinctrl-names = "default";
    689 	pinctrl-0 = <&i2c2_xfer>;
    690 };
    691 
    692 &i2c3 {
    693 	compatible = "rockchip,rk3188-i2c";
    694 	pinctrl-names = "default";
    695 	pinctrl-0 = <&i2c3_xfer>;
    696 };
    697 
    698 &i2c4 {
    699 	compatible = "rockchip,rk3188-i2c";
    700 	pinctrl-names = "default";
    701 	pinctrl-0 = <&i2c4_xfer>;
    702 };
    703 
    704 &pmu {
    705 	power: power-controller {
    706 		compatible = "rockchip,rk3188-power-controller";
    707 		#power-domain-cells = <1>;
    708 		#address-cells = <1>;
    709 		#size-cells = <0>;
    710 
    711 		power-domain@RK3188_PD_VIO {
    712 			reg = <RK3188_PD_VIO>;
    713 			clocks = <&cru ACLK_LCDC0>,
    714 				 <&cru ACLK_LCDC1>,
    715 				 <&cru DCLK_LCDC0>,
    716 				 <&cru DCLK_LCDC1>,
    717 				 <&cru HCLK_LCDC0>,
    718 				 <&cru HCLK_LCDC1>,
    719 				 <&cru SCLK_CIF0>,
    720 				 <&cru ACLK_CIF0>,
    721 				 <&cru HCLK_CIF0>,
    722 				 <&cru ACLK_IPP>,
    723 				 <&cru HCLK_IPP>,
    724 				 <&cru ACLK_RGA>,
    725 				 <&cru HCLK_RGA>;
    726 			pm_qos = <&qos_lcdc0>,
    727 				 <&qos_lcdc1>,
    728 				 <&qos_cif0>,
    729 				 <&qos_ipp>,
    730 				 <&qos_rga>;
    731 			#power-domain-cells = <0>;
    732 		};
    733 
    734 		power-domain@RK3188_PD_VIDEO {
    735 			reg = <RK3188_PD_VIDEO>;
    736 			clocks = <&cru ACLK_VDPU>,
    737 				 <&cru ACLK_VEPU>,
    738 				 <&cru HCLK_VDPU>,
    739 				 <&cru HCLK_VEPU>;
    740 			pm_qos = <&qos_vpu>;
    741 			#power-domain-cells = <0>;
    742 		};
    743 
    744 		power-domain@RK3188_PD_GPU {
    745 			reg = <RK3188_PD_GPU>;
    746 			clocks = <&cru ACLK_GPU>;
    747 			pm_qos = <&qos_gpu>;
    748 			#power-domain-cells = <0>;
    749 		};
    750 	};
    751 };
    752 
    753 &pwm0 {
    754 	pinctrl-names = "default";
    755 	pinctrl-0 = <&pwm0_out>;
    756 };
    757 
    758 &pwm1 {
    759 	pinctrl-names = "default";
    760 	pinctrl-0 = <&pwm1_out>;
    761 };
    762 
    763 &pwm2 {
    764 	pinctrl-names = "default";
    765 	pinctrl-0 = <&pwm2_out>;
    766 };
    767 
    768 &pwm3 {
    769 	pinctrl-names = "default";
    770 	pinctrl-0 = <&pwm3_out>;
    771 };
    772 
    773 &spi0 {
    774 	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
    775 	pinctrl-names = "default";
    776 	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
    777 };
    778 
    779 &spi1 {
    780 	compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
    781 	pinctrl-names = "default";
    782 	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
    783 };
    784 
    785 &uart0 {
    786 	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
    787 	pinctrl-names = "default";
    788 	pinctrl-0 = <&uart0_xfer>;
    789 };
    790 
    791 &uart1 {
    792 	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
    793 	pinctrl-names = "default";
    794 	pinctrl-0 = <&uart1_xfer>;
    795 };
    796 
    797 &uart2 {
    798 	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
    799 	pinctrl-names = "default";
    800 	pinctrl-0 = <&uart2_xfer>;
    801 };
    802 
    803 &uart3 {
    804 	compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
    805 	pinctrl-names = "default";
    806 	pinctrl-0 = <&uart3_xfer>;
    807 };
    808 
    809 &vpu {
    810 	compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu";
    811 	power-domains = <&power RK3188_PD_VIDEO>;
    812 };
    813 
    814 &wdt {
    815 	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
    816 };
    817