| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 704 u32 disp_clk; /* display clock in kHz */ member in struct:dce10_wm_params
816 fixed20_12 disp_clk, bandwidth; local
820 disp_clk.full = dfixed_const(wm->disp_clk);
821 disp_clk.full = dfixed_div(disp_clk, a);
823 b.full = dfixed_mul(a, disp_clk);
902 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
926 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
929 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000)
[all...] |
| amdgpu_dce_v11_0.c | 730 u32 disp_clk; /* display clock in kHz */ member in struct:dce10_wm_params
842 fixed20_12 disp_clk, bandwidth; local
846 disp_clk.full = dfixed_const(wm->disp_clk);
847 disp_clk.full = dfixed_div(disp_clk, a);
849 b.full = dfixed_mul(a, disp_clk);
928 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
952 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
955 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000)
[all...] |
| amdgpu_dce_v6_0.c | 502 u32 disp_clk; /* display clock in kHz */ member in struct:dce6_wm_params
614 fixed20_12 disp_clk, bandwidth; local
618 disp_clk.full = dfixed_const(wm->disp_clk);
619 disp_clk.full = dfixed_div(disp_clk, a);
621 b.full = dfixed_mul(a, disp_clk);
700 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
724 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
727 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000)
[all...] |
| amdgpu_dce_v8_0.c | 639 u32 disp_clk; /* display clock in kHz */ member in struct:dce8_wm_params
751 fixed20_12 disp_clk, bandwidth; local
755 disp_clk.full = dfixed_const(wm->disp_clk);
756 disp_clk.full = dfixed_div(disp_clk, a);
758 b.full = dfixed_mul(a, disp_clk);
837 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
861 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
864 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_si.c | 2068 u32 disp_clk; /* display clock in kHz */ member in struct:dce6_wm_params
2149 fixed20_12 disp_clk, sclk, bandwidth; local
2154 disp_clk.full = dfixed_const(wm->disp_clk);
2155 disp_clk.full = dfixed_div(disp_clk, a);
2157 b1.full = dfixed_mul(a, disp_clk);
2218 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
2242 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
2245 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000)
[all...] |
| radeon_evergreen.c | 1940 u32 disp_clk; /* display clock in kHz */ member in struct:evergreen_wm_params
2016 fixed20_12 disp_clk, bandwidth; local
2020 disp_clk.full = dfixed_const(wm->disp_clk);
2021 disp_clk.full = dfixed_div(disp_clk, a);
2026 bandwidth.full = dfixed_mul(a, disp_clk);
2073 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
2097 lb_fill_bw = min(dfixed_trunc(a), wm->disp_clk * wm->bytes_per_pixel / 1000);
2195 wm_high.disp_clk = mode->clock
[all...] |
| radeon_cik.c | 8985 u32 disp_clk; /* display clock in kHz */ member in struct:dce8_wm_params
9097 fixed20_12 disp_clk, bandwidth; local
9101 disp_clk.full = dfixed_const(wm->disp_clk);
9102 disp_clk.full = dfixed_div(disp_clk, a);
9104 b.full = dfixed_mul(a, disp_clk);
9183 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
9207 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
9210 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000)
[all...] |
| radeon_trinity_dpm.c | 1643 u64 disp_clk = rdev->clock.default_dispclk / 100; local
1649 dc_cac_value = (u32)((14213 * disp_clk * disp_clk * (u64)num_active_displays) >>
|
