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    Searched refs:display_config (Results 1 - 20 of 20) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_hardwaremanager.c 304 const struct amd_pp_display_configuration *display_config)
311 if (display_config == NULL)
315 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk);
317 for (index = 0; index < display_config->num_path_including_non_display; index++) {
318 if (display_config->displays[index].controller_id != 0)
332 display_config->cpu_pstate_separation_time,
333 display_config->cpu_cc6_disable,
334 display_config->cpu_pstate_disable,
335 display_config->nb_pstate_switch_disable);
amdgpu_vega12_hwmgr.c 1484 if ((hwmgr->display_config->num_display > 1) &&
1485 !hwmgr->display_config->multi_monitor_in_sync &&
1486 !hwmgr->display_config->nb_pstate_switch_disable)
1491 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
1492 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
1493 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2184 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
2185 !hwmgr->display_config->multi_monitor_in_sync) ||
2187 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
2238 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)
    [all...]
amdgpu_smu10_hwmgr.c 205 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
578 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
579 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
671 hwmgr->display_config->num_display > 3 ?
amdgpu_vega20_hwmgr.c 2310 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2311 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2312 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3574 hwmgr->display_config->num_display);
3648 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3649 !hwmgr->display_config->multi_monitor_in_sync) ||
3651 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3702 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3703 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3710 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100))
    [all...]
amdgpu_vega10_hwmgr.c 3218 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
3219 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3259 if (hwmgr->display_config->num_display == 0)
3262 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3263 !hwmgr->display_config->multi_monitor_in_sync) ||
3295 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3361 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3978 if ((hwmgr->display_config->num_display > 1) &&
3979 !hwmgr->display_config->multi_monitor_in_sync &&
3980 !hwmgr->display_config->nb_pstate_switch_disable
    [all...]
amdgpu_smu7_hwmgr.c 2931 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
2932 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2963 if (hwmgr->display_config->num_display == 0)
2966 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
2967 !hwmgr->display_config->multi_monitor_in_sync) ||
2969 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time);
3647 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4062 if (hwmgr->display_config->num_display > 1 &&
4063 !hwmgr->display_config->multi_monitor_in_sync)
4084 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE)
    [all...]
amdgpu_smu8_hwmgr.c 707 clock = hwmgr->display_config->min_core_set_clock;
762 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr;
1060 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ?
1061 hwmgr->display_config->min_mem_set_clock :
1069 || (hwmgr->display_config->num_display >= 3);
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_smu.c 931 smu->display_config = &adev->pm.pm_display_cfg;
1548 const struct amd_pp_display_configuration *display_config)
1556 if (!display_config)
1563 display_config->min_dcef_deep_sleep_set_clk / 100);
1565 for (index = 0; index < display_config->num_path_including_non_display; index++) {
1566 if (display_config->displays[index].controller_id != 0)
1572 smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1573 display_config->cpu_cc6_disable,
1574 display_config->cpu_pstate_disable,
1575 display_config->nb_pstate_switch_disable)
    [all...]
amdgpu_vega20_ppt.c 2084 smu->display_config->num_display);
2099 disable_mclk_switching = ((1 < smu->display_config->num_display) &&
2100 !smu->display_config->multi_monitor_in_sync) || vblank_too_short;
2101 latency = smu->display_config->dce_tolerable_mclk_in_active_latency;
2148 if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100))
2149 dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100;
2156 if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) {
2164 if (smu->display_config->nb_pstate_switch_disable)
2246 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2247 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk
    [all...]
amdgpu_amd_powerplay.c 62 hwmgr->display_config = &adev->pm.pm_display_cfg;
1053 const struct amd_pp_display_configuration *display_config)
1061 phm_store_dal_configuration_data(hwmgr, display_config);
amdgpu_navi10_ppt.c 1087 smu->display_config->num_display);
1464 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1465 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1466 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
hardwaremanager.h 433 const struct amd_pp_display_configuration *display_config);
amdgpu_smu.h 373 struct amd_pp_display_configuration *display_config; member in struct:smu_context
693 *display_config);
hwmgr.h 790 const struct amd_pp_display_configuration *display_config; member in struct:pp_hwmgr
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_fiji_smumgr.c 981 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
985 hwmgr->display_config->min_core_set_clock_in_sr);
1206 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1207 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
amdgpu_vegam_smumgr.c 841 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
845 hwmgr->display_config->min_core_set_clock_in_sr);
1015 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1016 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
amdgpu_iceland_smumgr.c 937 hwmgr->display_config->min_core_set_clock_in_sr;
1287 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1288 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
amdgpu_polaris10_smumgr.c 949 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
953 hwmgr->display_config->min_core_set_clock_in_sr);
1111 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1112 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
amdgpu_tonga_smumgr.c 664 hwmgr->display_config->min_core_set_clock_in_sr;
1021 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1022 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
amdgpu_ci_smumgr.c 1239 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1240 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;

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