| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_fiji_smumgr.c | 2568 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; local in function:fiji_update_dpm_settings
2597 down_hyst_offset = array + (sizeof(SMU73_Discrete_GraphicsLevel) * i)
2602 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
2632 down_hyst_offset = mclk_array + (sizeof(SMU73_Discrete_MemoryLevel) * i)
2637 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
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| amdgpu_ci_smumgr.c | 2779 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; local in function:ci_update_dpm_settings
2808 down_hyst_offset = array + (sizeof(SMU7_Discrete_GraphicsLevel) * i)
2813 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownH, sizeof(uint8_t));
2843 down_hyst_offset = mclk_array + (sizeof(SMU7_Discrete_MemoryLevel) * i)
2848 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownH, sizeof(uint8_t));
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| amdgpu_polaris10_smumgr.c | 2484 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; local in function:polaris10_update_dpm_settings
2513 down_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2518 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
2548 down_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2553 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
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| amdgpu_tonga_smumgr.c | 3167 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; local in function:tonga_update_dpm_settings
3196 down_hyst_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i)
3201 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
3231 down_hyst_offset = mclk_array + (sizeof(SMU72_Discrete_MemoryLevel) * i)
3236 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
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