| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_display.c | 580 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
592 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
594 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
597 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
609 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
621 int chv_calc_dpll_params(int refclk, struct dpll *clock)
642 const struct dpll *clock)
715 int target, int refclk, struct dpll *match_clock
1511 u32 dpll = crtc_state->dpll_hw_state.dpll; local in function:i9xx_enable_pll
8480 u32 dpll; local in function:i9xx_compute_dpll
8554 u32 dpll; local in function:i8xx_compute_dpll
10025 u32 dpll, fp, fp2; local in function:ilk_compute_dpll
11878 u32 dpll = pipe_config->dpll_hw_state.dpll; local in function:i9xx_pll_refclk
11897 u32 dpll = pipe_config->dpll_hw_state.dpll; local in function:i9xx_crtc_clock_get
17703 u32 dpll, fp; local in function:i830_enable_pipe
[all...] |
| intel_dvo.c | 452 u32 dpll[I915_MAX_PIPES]; local in function:intel_dvo_init
489 dpll[pipe] = I915_READ(DPLL(pipe));
490 I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE);
497 I915_WRITE(DPLL(pipe), dpll[pipe]);
|
| intel_display.h | 54 struct dpll;
575 const struct dpll *dpll);
588 struct dpll *best_clock);
589 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
|
| intel_dpll_mgr.h | 51 * enum intel_dpll_id - possible DPLL ids
53 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
57 * @DPLL_ID_PRIVATE: non-shared dpll in use
62 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
66 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
172 u32 dpll; member in struct:intel_dpll_hw_state
183 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
186 * the DPLL.
218 * struct intel_shared_dpll_state - hold the DPLL atomic stat
[all...] |
| intel_display_types.h | 447 struct dpll { struct
898 /* Settings for the intel dpll used on pretty much everything but
900 struct dpll dpll; member in struct:intel_crtc_state
902 /* Selected dpll when shared or NULL. */
905 /* Actual register state of the dpll, for shared dpll cross-checking. */
934 * Frequence the dpll for the port should run at. Differs from the
|
| intel_dpll_mgr.c | 61 /* Copy shared dpll state */
87 * intel_get_shared_dpll_by_id - get a DPLL given its id
92 * A pointer to the DPLL with @id
102 * intel_get_shared_dpll_id - get the id of a DPLL
104 * @pll: the DPLL
128 if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
138 * intel_prepare_shared_dpll - call a dpll's prepare hook
139 * @crtc_state: CRTC, and its state, which has a shared dpll
166 * intel_enable_shared_dpll - enable a CRTC's shared DPLL
[all...] |
| intel_dp.c | 92 struct dpll dpll; member in struct:dp_link_dpll
791 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
794 * The DPLL for the pipe must be enabled for this to work.
802 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
1816 pipe_config->dpll = divisor[i].dpll;
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| intel_sdvo.c | 1250 struct dpll *clock = &pipe_config->dpll;
1543 /* done in crtc_mode_set as it lives inside the dpll register */
1641 * the sdvo port register, on all other platforms it is part of the dpll
|
| intel_ddi.c | 1722 struct dpll clock;
3122 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| omap54xx-clocks.dtsi | 104 compatible = "ti,omap4-dpll-m4xen-clock";
111 compatible = "ti,omap4-dpll-x2-clock";
177 compatible = "ti,omap4-dpll-core-clock";
184 compatible = "ti,omap4-dpll-x2-clock";
312 compatible = "ti,omap4-dpll-clock";
321 compatible = "ti,omap4-dpll-x2-clock";
357 compatible = "ti,omap5-mpu-dpll-clock";
521 compatible = "ti,omap4-dpll-clock";
528 compatible = "ti,omap4-dpll-x2-clock";
588 compatible = "ti,omap4-dpll-clock"
[all...] |
| am43xx-clocks.dtsi | 205 compatible = "ti,am3-dpll-core-clock";
212 compatible = "ti,am3-dpll-x2-clock";
251 compatible = "ti,am3-dpll-clock";
277 compatible = "ti,am3-dpll-clock";
295 compatible = "ti,am3-dpll-clock";
314 compatible = "ti,am3-dpll-j-type-clock";
558 compatible = "ti,am3-dpll-clock";
627 compatible = "ti,am3-dpll-x2-clock";
|
| dra7xx-clocks.dtsi | 198 compatible = "ti,omap4-dpll-m4xen-clock";
205 compatible = "ti,omap4-dpll-x2-clock";
261 compatible = "ti,omap4-dpll-core-clock";
268 compatible = "ti,omap4-dpll-x2-clock";
293 compatible = "ti,omap5-mpu-dpll-clock";
335 compatible = "ti,omap4-dpll-clock";
373 compatible = "ti,omap4-dpll-clock";
411 compatible = "ti,omap4-dpll-clock";
460 compatible = "ti,omap4-dpll-clock";
486 compatible = "ti,omap4-dpll-clock"
[all...] |
| omap36xx-clocks.dtsi | 10 compatible = "ti,omap3-dpll-per-j-type-clock";
|
| am33xx-clocks.dtsi | 165 compatible = "ti,am3-dpll-core-clock";
172 compatible = "ti,am3-dpll-x2-clock";
205 compatible = "ti,am3-dpll-clock";
221 compatible = "ti,am3-dpll-no-gate-clock";
245 compatible = "ti,am3-dpll-no-gate-clock";
262 compatible = "ti,am3-dpll-no-gate-j-type-clock";
|
| imx6q-dms-ba16.dts | 117 fsl,receive-dpll-mode = <1>;
|
| omap44xx-clocks.dtsi | 134 compatible = "ti,omap4-dpll-m4xen-clock";
141 compatible = "ti,omap4-dpll-x2-clock";
196 compatible = "ti,omap4-dpll-core-clock";
203 compatible = "ti,omap4-dpll-x2-clock";
346 compatible = "ti,omap4-dpll-clock";
355 compatible = "ti,omap4-dpll-x2-clock";
387 compatible = "ti,omap4-dpll-clock";
566 compatible = "ti,omap4-dpll-clock";
582 compatible = "ti,omap4-dpll-x2-clock";
667 compatible = "ti,omap4-dpll-j-type-clock"
[all...] |
| omap34xx-omap36xx-clocks.dtsi | 165 compatible = "ti,omap3-dpll-clock";
|
| omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 27 compatible = "ti,omap3-dpll-clock";
|
| omap3xxx-clocks.dtsi | 195 compatible = "ti,omap3-dpll-per-clock";
236 compatible = "ti,omap3-dpll-core-clock";
318 compatible = "ti,omap3-dpll-clock";
|
| omap24xx-clocks.dtsi | 123 compatible = "ti,omap2-dpll-core-clock";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/sprd/ |
| sharkl3.dtsi | 123 dpll: dpll { label in label:soc.anlg_phy_g7_regs
124 compatible = "sprd,sc9863a-dpll";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/microchip/ |
| sparx5.dtsi | 84 compatible = "microchip,sparx5-dpll";
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/ |
| salvator-common.dtsi | 524 reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_drv.h | 266 struct dpll;
1098 /* dpll and cdclk state is protected by connection_mutex */
1105 * Must be global rather than per dpll, because on some platforms
|
| i915_debugfs.c | 2751 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
2756 seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll);
|
