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    Searched refs:dpm_level_enable_mask (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_ci_dpm.c 2650 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
3311 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3365 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3829 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3832 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3839 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3842 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3849 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3852 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3949 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0
    [all...]
ci_dpm.h 240 struct ci_dpm_level_enable_mask dpm_level_enable_mask; member in struct:ci_power_info
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu7_hwmgr.c 2612 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2614 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
2625 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2627 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
2639 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2641 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
2664 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
2667 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2671 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
2674 data->dpm_level_enable_mask.mclk_dpm_enable_mask)
    [all...]
smu7_hwmgr.h 296 struct smu7_dpmlevel_enable_mask dpm_level_enable_mask; member in struct:smu7_hwmgr
vega10_hwmgr.h 371 struct vega10_dpmlevel_enable_mask dpm_level_enable_mask; member in struct:vega10_hwmgr
vega12_hwmgr.h 374 struct vega12_dpmlevel_enable_mask dpm_level_enable_mask; member in struct:vega12_hwmgr
vega20_hwmgr.h 498 struct vega20_dpmlevel_enable_mask dpm_level_enable_mask; member in struct:vega20_hwmgr
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_vegam_smumgr.c 598 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
912 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
917 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1;
928 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
929 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
933 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
934 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
939 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1070 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1075 (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1
    [all...]
amdgpu_fiji_smumgr.c 856 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1050 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1062 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1063 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1067 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1068 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1073 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1265 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
amdgpu_iceland_smumgr.c 794 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1007 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1010 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1015 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1021 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1388 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
amdgpu_ci_smumgr.c 505 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1020 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1343 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2881 data->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
2885 data->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
2890 data->dpm_level_enable_mask.uvd_dpm_enable_mask);
2912 data->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
2916 data->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
2921 data->dpm_level_enable_mask.vce_dpm_enable_mask);
amdgpu_tonga_smumgr.c 537 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
737 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
750 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
753 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
754 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
759 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
760 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
766 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1136 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
amdgpu_polaris10_smumgr.c 796 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1025 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1038 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1039 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1043 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1044 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1049 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1169 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =

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