| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| dccg.h | 42 int dpp_inst,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dccg.c | 52 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
69 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
73 DPPCLK_DTO_ENABLE[dpp_inst], 1);
76 DPPCLK_DTO_ENABLE[dpp_inst], 0);
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| dcn20_dccg.h | 102 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
|
| dcn20_hwseq.h | 97 unsigned int dpp_inst,
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| amdgpu_dcn20_hwseq.c | 410 unsigned int dpp_inst,
421 switch (dpp_inst) {
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dmub_psr.c | 151 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
153 copy_settings_data->dpp_inst = 0;
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| hw_sequencer_private.h | 115 unsigned int dpp_inst,
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/inc/ |
| dmub_cmd.h | 222 uint8_t dpp_inst; member in struct:dmub_cmd_psr_copy_settings_data
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/ |
| amdgpu_dcn20_clk_mgr.c | 115 int dpp_inst, dppclk_khz, prev_dppclk_khz; local in function:dcn20_update_clocks_update_dpp_dto
120 dpp_inst = i;
127 clk_mgr->dccg, dpp_inst, dppclk_khz);
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| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| dcn10_hw_sequencer.h | 86 unsigned int dpp_inst,
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| amdgpu_dcn10_hw_sequencer.c | 540 unsigned int dpp_inst,
551 switch (dpp_inst) {
|
