1 /* $NetBSD: dcn20_hwseq.h,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef __DC_HWSS_DCN20_H__ 29 #define __DC_HWSS_DCN20_H__ 30 31 #include "hw_sequencer_private.h" 32 33 bool dcn20_set_blend_lut( 34 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); 35 bool dcn20_set_shaper_3dlut( 36 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); 37 void dcn20_program_front_end_for_ctx( 38 struct dc *dc, 39 struct dc_state *context); 40 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx); 41 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx); 42 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 43 const struct dc_plane_state *plane_state); 44 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 45 const struct dc_stream_state *stream); 46 void dcn20_program_output_csc(struct dc *dc, 47 struct pipe_ctx *pipe_ctx, 48 enum dc_color_space colorspace, 49 uint16_t *matrix, 50 int opp_id); 51 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx); 52 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 53 struct dc_link_settings *link_settings); 54 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx); 55 void dcn20_blank_pixel_data( 56 struct dc *dc, 57 struct pipe_ctx *pipe_ctx, 58 bool blank); 59 void dcn20_pipe_control_lock( 60 struct dc *dc, 61 struct pipe_ctx *pipe, 62 bool lock); 63 void dcn20_pipe_control_lock_global( 64 struct dc *dc, 65 struct pipe_ctx *pipe, 66 bool lock); 67 void dcn20_prepare_bandwidth( 68 struct dc *dc, 69 struct dc_state *context); 70 void dcn20_optimize_bandwidth( 71 struct dc *dc, 72 struct dc_state *context); 73 bool dcn20_update_bandwidth( 74 struct dc *dc, 75 struct dc_state *context); 76 void dcn20_reset_hw_ctx_wrap( 77 struct dc *dc, 78 struct dc_state *context); 79 enum dc_status dcn20_enable_stream_timing( 80 struct pipe_ctx *pipe_ctx, 81 struct dc_state *context, 82 struct dc *dc); 83 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx); 84 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx); 85 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx); 86 void dcn20_init_blank( 87 struct dc *dc, 88 struct timing_generator *tg); 89 void dcn20_disable_vga( 90 struct dce_hwseq *hws); 91 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx); 92 void dcn20_enable_power_gating_plane( 93 struct dce_hwseq *hws, 94 bool enable); 95 void dcn20_dpp_pg_control( 96 struct dce_hwseq *hws, 97 unsigned int dpp_inst, 98 bool power_on); 99 void dcn20_hubp_pg_control( 100 struct dce_hwseq *hws, 101 unsigned int hubp_inst, 102 bool power_on); 103 void dcn20_program_triple_buffer( 104 const struct dc *dc, 105 struct pipe_ctx *pipe_ctx, 106 bool enable_triple_buffer); 107 void dcn20_enable_writeback( 108 struct dc *dc, 109 struct dc_writeback_info *wb_info, 110 struct dc_state *context); 111 void dcn20_disable_writeback( 112 struct dc *dc, 113 unsigned int dwb_pipe_inst); 114 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); 115 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx); 116 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx); 117 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx); 118 void dcn20_init_vm_ctx( 119 struct dce_hwseq *hws, 120 struct dc *dc, 121 struct dc_virtual_addr_space_config *va_config, 122 int vmid); 123 void dcn20_set_flip_control_gsl( 124 struct pipe_ctx *pipe_ctx, 125 bool flip_immediate); 126 void dcn20_dsc_pg_control( 127 struct dce_hwseq *hws, 128 unsigned int dsc_inst, 129 bool power_on); 130 void dcn20_fpga_init_hw(struct dc *dc); 131 bool dcn20_wait_for_blank_complete( 132 struct output_pixel_processor *opp); 133 void dcn20_dccg_init(struct dce_hwseq *hws); 134 int dcn20_init_sys_ctx(struct dce_hwseq *hws, 135 struct dc *dc, 136 struct dc_phy_addr_space_config *pa_config); 137 138 #endif /* __DC_HWSS_DCN20_H__ */ 139 140
Indexes created Tue Sep 30 11:09:46 GMT 2025