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    Searched refs:dram_clock_change_latency_us (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_socbb.h 73 uint32_t dram_clock_change_latency_us; member in struct:gpu_info_soc_bounding_box_v1_0
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
display_mode_structs.h 106 double dram_clock_change_latency_us; member in struct:_vcs_dpi_soc_bounding_box_st
amdgpu_display_mode_vba.c 228 mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us;
229 mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us;
amdgpu_dml1_display_rq_dlg_calc.c 1295 mode_lib->soc.dram_clock_change_latency_us
1309 "DLG: %s: soc.dram_clock_change_latency_us = %3.2f",
1311 (double) mode_lib->soc.dram_clock_change_latency_us);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 333 .dram_clock_change_latency_us = 404.0,
2941 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
2963 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
2977 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
3288 if ((int)(bb->dram_clock_change_latency_us * 1000)
3291 bb->dram_clock_change_latency_us =
3404 dcn2_0_nv12_soc.dram_clock_change_latency_us =
3405 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
3407 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_resource.c 268 .dram_clock_change_latency_us = 23.84,
986 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
994 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
1006 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_resource.c 134 .dram_clock_change_latency_us = 17.0,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
amdgpu_display_rq_dlg_calc_20.c 1085 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us
amdgpu_display_rq_dlg_calc_20v2.c 1086 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
amdgpu_display_rq_dlg_calc_21.c 1133 mode_lib->soc.dram_clock_change_latency_us
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 1720 dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency;

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