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      1 /*	$NetBSD: amdgpu_socbb.h,v 1.2 2021/12/18 23:44:58 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2019 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 #ifndef __AMDGPU_SOCBB_H__
     26 #define __AMDGPU_SOCBB_H__
     27 
     28 struct gpu_info_voltage_scaling_v1_0 {
     29 	uint32_t state;
     30 	uint32_t dscclk_mhz;
     31 	uint32_t dcfclk_mhz;
     32 	uint32_t socclk_mhz;
     33 	uint32_t dram_speed_mts;
     34 	uint32_t fabricclk_mhz;
     35 	uint32_t dispclk_mhz;
     36 	uint32_t phyclk_mhz;
     37 	uint32_t dppclk_mhz;
     38 };
     39 
     40 struct gpu_info_soc_bounding_box_v1_0 {
     41 	uint32_t sr_exit_time_us;
     42 	uint32_t sr_enter_plus_exit_time_us;
     43 	uint32_t urgent_latency_us;
     44 	uint32_t urgent_latency_pixel_data_only_us;
     45 	uint32_t urgent_latency_pixel_mixed_with_vm_data_us;
     46 	uint32_t urgent_latency_vm_data_only_us;
     47 	uint32_t writeback_latency_us;
     48 	uint32_t ideal_dram_bw_after_urgent_percent;
     49 	uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
     50 	uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
     51 	uint32_t pct_ideal_dram_sdp_bw_after_urgent_vm_only;
     52 	uint32_t max_avg_sdp_bw_use_normal_percent;
     53 	uint32_t max_avg_dram_bw_use_normal_percent;
     54 	uint32_t max_request_size_bytes;
     55 	uint32_t downspread_percent;
     56 	uint32_t dram_page_open_time_ns;
     57 	uint32_t dram_rw_turnaround_time_ns;
     58 	uint32_t dram_return_buffer_per_channel_bytes;
     59 	uint32_t dram_channel_width_bytes;
     60 	uint32_t fabric_datapath_to_dcn_data_return_bytes;
     61 	uint32_t dcn_downspread_percent;
     62 	uint32_t dispclk_dppclk_vco_speed_mhz;
     63 	uint32_t dfs_vco_period_ps;
     64 	uint32_t urgent_out_of_order_return_per_channel_pixel_only_bytes;
     65 	uint32_t urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
     66 	uint32_t urgent_out_of_order_return_per_channel_vm_only_bytes;
     67 	uint32_t round_trip_ping_latency_dcfclk_cycles;
     68 	uint32_t urgent_out_of_order_return_per_channel_bytes;
     69 	uint32_t channel_interleave_bytes;
     70 	uint32_t num_banks;
     71 	uint32_t num_chans;
     72 	uint32_t vmm_page_size_bytes;
     73 	uint32_t dram_clock_change_latency_us;
     74 	uint32_t writeback_dram_clock_change_latency_us;
     75 	uint32_t return_bus_width_bytes;
     76 	uint32_t voltage_override;
     77 	uint32_t xfc_bus_transport_time_us;
     78 	uint32_t xfc_xbuf_latency_tolerance_us;
     79 	uint32_t use_urgent_burst_bw;
     80 	uint32_t num_states;
     81 	struct gpu_info_voltage_scaling_v1_0 clock_limits[8];
     82 };
     83 
     84 #endif
     85