| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dsb.c | 20 * DOC: DSB
22 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
23 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
24 * engine that can be programmed to download the DSB from memory.
27 * faster. DSB Support added from Gen12 Intel graphics based platform.
29 * DSB's can access only the pipe, plane, and transcoder Data Island Packet
32 * DSB HW can support only register writes (both indexed and direct MMIO
33 * writes). There are no registers reads possible with DSB HW engine.
36 /* DSB opcodes. *
109 struct intel_dsb *dsb = &crtc->dsb; local
[all...] |
| intel_dsb.h | 39 * ins_start_offset will help to store start address of the dsb
48 void intel_dsb_put(struct intel_dsb *dsb);
49 void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
50 void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
52 void intel_dsb_commit(struct intel_dsb *dsb);
|
| intel_color.c | 635 struct intel_dsb *dsb = intel_dsb_get(crtc); local
639 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
640 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
641 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
649 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
651 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
653 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
657 intel_dsb_put(dsb);
817 struct intel_dsb *dsb = intel_dsb_get(crtc); local
821 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red)
833 struct intel_dsb *dsb = intel_dsb_get(crtc); local
866 struct intel_dsb *dsb = intel_dsb_get(crtc); local
920 struct intel_dsb *dsb = intel_dsb_get(crtc); local
[all...] |
| /src/sys/arch/aarch64/aarch64/ |
| cpufunc_asm_armv8.S | 68 dsb ish
80 dsb ish
150 dsb ishst
159 dsb ish
165 dsb ish
173 dsb sy
184 dsb ish
186 dsb ish
197 dsb ish
201 dsb ns
[all...] |
| idle_machdep.S | 58 dsb sy
100 dsb sy
|
| cpufunc.c | 320 __asm __volatile ("dc csw, %0; dsb sy" :: "r"(x));
338 __asm __volatile ("dc cisw, %0; dsb sy" :: "r"(x));
356 __asm __volatile ("dc isw, %0; dsb sy" :: "r"(x));
374 dsb(ish);
377 dsb(ish);
393 dsb(ish);
396 dsb(ish);
412 dsb(ish);
415 dsb(ish);
|
| bus_space.c | 643 * should enforce ordering or completion. To be safe, use dsb
648 dsb(ld);
651 dsb(st);
654 dsb(sy);
705 dsb(ld);
720 dsb(ld);
735 dsb(ld);
750 dsb(ld);
|
| locore.S | 287 dsb sy
289 dsb sy
326 dsb sy
486 dsb ish
905 dsb sy
913 dsb sy
916 dsb ishst
922 dsb ish
|
| /src/sys/external/bsd/common/include/asm/ |
| barrier.h | 55 #define mb() dsb(sy)
56 #define wmb() dsb(st)
57 #define rmb() dsb(ld)
60 #define mb() dsb()
|
| /src/sys/arch/arm/samsung/ |
| exynos_smc.S | 48 dsb /* Data Synchronisation Barrier */
|
| /src/sys/arch/arm/ti/ |
| omap_smc.S | 74 dsb /* Data Synchronisation Barrier */
|
| /src/sys/arch/aarch64/include/ |
| asm.h | 30 eret; dsb sy; isb
|
| /src/sys/arch/arm/arm32/ |
| arm32_tlb.c | 55 dsb(sy);
68 dsb(sy);
82 dsb(sy);
96 dsb(sy);
105 dsb(sy);
127 dsb(sy);
|
| db_interface.c | 180 dsb(ishst);
193 dsb(ishst);
|
| /src/sys/stand/efiboot/bootaa64/ |
| cache.S | 70 dsb ish
73 dsb ish
96 dsb ish
98 dsb ish
|
| /src/sys/arch/arm/arm/ |
| cpu_subr.c | 89 dsb(ishst);
130 dsb(ishst);
144 dsb(ishst);
|
| cpufunc_asm_armv7.S | 37 dsb
49 dsb @ data synchronization barrier
61 dsb
69 dsb @ data synchronization barrier
77 dsb @ data synchronization barrier
93 dsb @ data synchronization barrier
108 dsb @ data synchronization barrier
120 dsb @ data synchronization barrier
127 dsb
131 dsb @ data synchronization barrie
[all...] |
| cpufunc_asm_pj4b.S | 56 dsb
58 dsb @ Erratum#ARM-CPU-4742
117 dsb
|
| /src/sys/arch/arm/include/ |
| cpufunc.h | 47 * Options for DMB and DSB:
61 #define dsb(opt) __asm __volatile("dsb " __STRING(opt) : : : "memory") macro
68 #define dsb(opt) \ macro
79 #define dma_r_r() dsb(oshld) // actually r_rw
80 #define dma_w_w() dsb(oshst)
81 #define dma_rw_w() dsb(osh) // actually rw_rw
83 #define dma_r_r() dsb(osh) // actually rw_rw
84 #define dma_w_w() dsb(oshst)
85 #define dma_rw_w() dsb(osh) // actually rw_r
[all...] |
| /src/sys/stand/efiboot/bootarm/ |
| cache.S | 46 dsb
52 dsb @ data synchronization barrier
102 dsb
112 dsb
148 2: dsb @ wait for stores to finish
165 dsb
168 dsb
|
| /src/sys/arch/evbarm/armadaxp/ |
| armadaxp_start.S | 78 dsb
131 dsb
|
| /src/sys/arch/arm/fdt/ |
| arm_platform.c | 94 dsb(sy);
|
| /src/sys/arch/arm/imx/ |
| imx23_platform.c | 78 dsb(sy);
|
| /src/sys/arch/arm/rockchip/ |
| rk3066_smp.c | 132 dsb();
|
| /src/sys/external/bsd/vchiq/dist/interface/vchiq_arm/ |
| vchiq_kmod_netbsd.c | 101 dsb(sy); /* data barrier operation */
|
