| /src/external/ibm-public/postfix/dist/src/global/ |
| dsn_buf.c | 29 /* DSN_BUF *dsb_update(dsb, status, action, mtype, mname, dtype,
31 /* DSN_BUF *dsb;
40 /* DSN_BUF *dsb_simple(dsb, status, reason_fmt, ...)
41 /* DSN_BUF *dsb;
45 /* DSN_BUF *dsb_unix(dsb, status, dtext, reason_fmt, ...)
46 /* DSN_BUF *dsb;
50 /* DSN_BUF *dsb_formal(dsb, status, action, mtype, mname, dtype,
52 /* DSN_BUF *dsb;
60 /* DSN_BUF *dsb_status(dsb, status)
61 /* DSN_BUF *dsb;
173 DSN_BUF *dsb; local
[all...] |
| dsb_scan.c | 58 DSN_BUF *dsb = (DSN_BUF *) ptr; local
66 RECV_ATTR_STR(MAIL_ATTR_DSN_STATUS, dsb->status),
67 RECV_ATTR_STR(MAIL_ATTR_DSN_DTYPE, dsb->dtype),
68 RECV_ATTR_STR(MAIL_ATTR_DSN_DTEXT, dsb->dtext),
69 RECV_ATTR_STR(MAIL_ATTR_DSN_MTYPE, dsb->mtype),
70 RECV_ATTR_STR(MAIL_ATTR_DSN_MNAME, dsb->mname),
71 RECV_ATTR_STR(MAIL_ATTR_DSN_ACTION, dsb->action),
72 RECV_ATTR_STR(MAIL_ATTR_WHY, dsb->reason),
|
| dsn_buf.h | 70 #define DSN_FROM_DSN_BUF(dsb) \
71 DSN_ASSIGN(&(dsb)->dsn, \
72 vstring_str((dsb)->status), \
73 vstring_str((dsb)->action), \
74 vstring_str((dsb)->reason), \
75 vstring_str((dsb)->dtype), \
76 vstring_str((dsb)->dtext), \
77 vstring_str((dsb)->mtype), \
78 vstring_str((dsb)->mname))
|
| deliver_pass.c | 152 static int deliver_pass_final_reply(VSTREAM *stream, DSN_BUF *dsb)
157 RECV_ATTR_FUNC(dsb_scan, (void *) dsb),
174 DSN_BUF *dsb; local
198 dsb = dsb_create();
216 } else if ((status = deliver_pass_final_reply(stream, dsb))
228 dsb_free(dsb);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dsb.c | 20 * DOC: DSB
22 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
23 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
24 * engine that can be programmed to download the DSB from memory.
27 * faster. DSB Support added from Gen12 Intel graphics based platform.
29 * DSB's can access only the pipe, plane, and transcoder Data Island Packet
32 * DSB HW can support only register writes (both indexed and direct MMIO
33 * writes). There are no registers reads possible with DSB HW engine.
36 /* DSB opcodes. *
109 struct intel_dsb *dsb = &crtc->dsb; local
[all...] |
| intel_dsb.h | 39 * ins_start_offset will help to store start address of the dsb
48 void intel_dsb_put(struct intel_dsb *dsb);
49 void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
50 void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
52 void intel_dsb_commit(struct intel_dsb *dsb);
|
| intel_color.c | 635 struct intel_dsb *dsb = intel_dsb_get(crtc); local
639 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
640 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
641 intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
649 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
651 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
653 intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
657 intel_dsb_put(dsb);
817 struct intel_dsb *dsb = intel_dsb_get(crtc); local
821 intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red)
833 struct intel_dsb *dsb = intel_dsb_get(crtc); local
866 struct intel_dsb *dsb = intel_dsb_get(crtc); local
920 struct intel_dsb *dsb = intel_dsb_get(crtc); local
[all...] |
| /src/sys/arch/aarch64/aarch64/ |
| cpufunc_asm_armv8.S | 68 dsb ish
80 dsb ish
150 dsb ishst
159 dsb ish
165 dsb ish
173 dsb sy
184 dsb ish
186 dsb ish
197 dsb ish
201 dsb ns
[all...] |
| idle_machdep.S | 58 dsb sy
100 dsb sy
|
| /src/sys/external/bsd/common/include/asm/ |
| barrier.h | 55 #define mb() dsb(sy)
56 #define wmb() dsb(st)
57 #define rmb() dsb(ld)
60 #define mb() dsb()
|
| /src/external/gpl3/gcc/dist/gcc/config/nds32/ |
| nds32_init.inc | 31 dsb
37 dsb
|
| /src/external/gpl3/gcc.old/dist/gcc/config/nds32/ |
| nds32_init.inc | 31 dsb
37 dsb
|
| /src/external/ibm-public/postfix/dist/src/oqmgr/ |
| qmgr_deliver.c | 126 static int qmgr_deliver_final_reply(VSTREAM *stream, DSN_BUF *dsb)
134 RECV_ATTR_FUNC(dsb_scan, (void *) dsb),
252 static DSN_BUF *dsb; local
265 if (dsb == 0)
266 dsb = dsb_create();
280 status = qmgr_deliver_final_reply(entry->stream, dsb);
298 DSN_SIMPLE(&dsb->dsn, "4.3.0", whatsup));
302 DSN_SIMPLE(&dsb->dsn, "4.3.0",
323 qmgr_defer_transport(transport, &dsb->dsn);
342 (void) DSN_SIMPLE(&dsb->dsn, "4.3.0", "unknown mail transport error")
[all...] |
| /src/external/ibm-public/postfix/dist/src/qmgr/ |
| qmgr_deliver.c | 131 static int qmgr_deliver_final_reply(VSTREAM *stream, DSN_BUF *dsb)
139 RECV_ATTR_FUNC(dsb_scan, (void *) dsb),
257 static DSN_BUF *dsb; local
270 if (dsb == 0)
271 dsb = dsb_create();
285 status = qmgr_deliver_final_reply(entry->stream, dsb);
303 DSN_SIMPLE(&dsb->dsn, "4.3.0", whatsup));
307 DSN_SIMPLE(&dsb->dsn, "4.3.0",
328 qmgr_defer_transport(transport, &dsb->dsn);
347 (void) DSN_SIMPLE(&dsb->dsn, "4.3.0", "unknown mail transport error")
[all...] |
| /src/sys/arch/arm/samsung/ |
| exynos_smc.S | 48 dsb /* Data Synchronisation Barrier */
|
| /src/sys/arch/arm/ti/ |
| omap_smc.S | 74 dsb /* Data Synchronisation Barrier */
|
| /src/sys/arch/aarch64/include/ |
| asm.h | 30 eret; dsb sy; isb
|
| /src/sys/arch/arm/arm32/ |
| arm32_tlb.c | 57 dsb(sy);
71 dsb(sy);
85 dsb(sy);
99 dsb(sy);
108 dsb(sy);
130 dsb(sy);
|
| /src/sys/stand/efiboot/bootaa64/ |
| cache.S | 70 dsb ish
73 dsb ish
96 dsb ish
98 dsb ish
|
| /src/external/gpl3/gcc/dist/libgcc/config/nds32/isr-library/ |
| reset.S | 93 dsb
102 dsb
129 dsb
135 dsb
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/nds32/isr-library/ |
| reset.S | 93 dsb
102 dsb
129 dsb
135 dsb
|
| /src/sys/arch/arm/arm/ |
| cpu_subr.c | 89 dsb(ishst);
130 dsb(ishst);
144 dsb(ishst);
|
| cpufunc_asm_armv7.S | 37 dsb
49 dsb @ data synchronization barrier
61 dsb
69 dsb @ data synchronization barrier
77 dsb @ data synchronization barrier
93 dsb @ data synchronization barrier
108 dsb @ data synchronization barrier
120 dsb @ data synchronization barrier
127 dsb
131 dsb @ data synchronization barrie
[all...] |
| cpufunc_asm_pj4b.S | 56 dsb
58 dsb @ Erratum#ARM-CPU-4742
117 dsb
|
| /src/sys/stand/efiboot/bootarm/ |
| cache.S | 46 dsb
52 dsb @ data synchronization barrier
102 dsb
112 dsb
148 2: dsb @ wait for stores to finish
165 dsb
168 dsb
|
