| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_dsc.c | 64 * @dsc_cfg:
76 const struct drm_dsc_config *dsc_cfg)
88 dsc_cfg->dsc_version_minor |
89 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
95 dsc_cfg->line_buf_depth |
96 dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
100 ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
102 dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
103 dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
104 dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/ |
| amdgpu_rc_calc_dpi.c | 79 static void copy_rc_to_cfg(struct drm_dsc_config *dsc_cfg, const struct rc_params *rc)
83 dsc_cfg->rc_quant_incr_limit0 = rc->rc_quant_incr_limit0;
84 dsc_cfg->rc_quant_incr_limit1 = rc->rc_quant_incr_limit1;
85 dsc_cfg->initial_offset = rc->initial_fullness_offset;
86 dsc_cfg->initial_xmit_delay = rc->initial_xmit_delay;
87 dsc_cfg->first_line_bpg_offset = rc->first_line_bpg_offset;
88 dsc_cfg->second_line_bpg_offset = rc->second_line_bpg_offset;
89 dsc_cfg->flatness_min_qp = rc->flatness_min_qp;
90 dsc_cfg->flatness_max_qp = rc->flatness_max_qp;
92 dsc_cfg->rc_range_params[i].range_min_qp = rc->qp_min[i]
119 struct drm_dsc_config dsc_cfg; local in function:dscc_compute_dsc_parameters
[all...] |
| amdgpu_dc_dsc.c | 47 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
553 * dsc_cfg - DSC configuration to use if it was possible to come up with
556 * dsc_cfg.bits_per_pixel (in U6.4 format) by pixel rate, e.g.
558 * dsc_stream_bitrate_kbps = (int)ceil(timing->pix_clk_khz * dsc_cfg.bits_per_pixel / 16.0);
566 struct dc_dsc_config *dsc_cfg)
582 memset(dsc_cfg, 0, sizeof(struct dc_dsc_config));
606 dsc_cfg->bits_per_pixel = target_bpp;
616 dsc_cfg->ycbcr422_simple = false;
634 dsc_cfg->ycbcr422_simple = is_dsc_possible;
732 dsc_cfg->num_slices_h = num_slices_h
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dsc.c | 36 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
47 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
48 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
50 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps);
168 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
173 if (dsc_cfg->pic_width > dsc20->max_image_width)
176 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg);
191 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
199 dsc_config_log(dsc, dsc_cfg);
200 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg)
[all...] |
| amdgpu_dcn20_resource.c | 1928 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
2055 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
2293 struct dsc_config dsc_cfg; local in function:dcn20_validate_dsc
2304 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2306 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2308 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2309 dsc_cfg.color_depth = stream->timing.display_color_depth;
2310 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2311 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt
[all...] |
| amdgpu_dcn20_stream_encoder.c | 447 && !timing->dsc_cfg.ycbcr422_simple);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| dsc.h | 92 bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
93 void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
95 bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_link_hwss.c | 428 struct dsc_config dsc_cfg; local in function:dp_set_dsc_on_stream
433 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
434 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
435 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
436 dsc_cfg.color_depth = stream->timing.display_color_depth;
437 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
438 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
439 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
441 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg)
530 struct dsc_config dsc_cfg; local in function:dp_set_dsc_pps_sdp
[all...] |
| amdgpu_dc_stream.c | 114 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
115 stream->timing.dsc_cfg.num_slices_h = 0;
116 stream->timing.dsc_cfg.num_slices_v = 0;
117 stream->timing.dsc_cfg.bits_per_pixel = 128;
118 stream->timing.dsc_cfg.block_pred_enable = 1;
119 stream->timing.dsc_cfg.linebuf_depth = 9;
120 stream->timing.dsc_cfg.version_minor = 2;
121 stream->timing.dsc_cfg.ycbcr422_simple = 0;
|
| amdgpu_dc.c | 2016 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
2027 stream->timing.dsc_cfg = *update->dsc_config;
2030 stream->timing.dsc_cfg = old_dsc_cfg;
|
| amdgpu_dc_link.c | 3200 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_dsc.h | 78 struct dc_dsc_config *dsc_cfg);
|
| dc_hw_types.h | 740 struct dc_dsc_config dsc_cfg; member in struct:dc_crtc_timing
|
| /src/sys/external/bsd/drm2/dist/include/drm/ |
| drm_dsc.h | 608 const struct drm_dsc_config *dsc_cfg);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm_mst_types.c | 552 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
559 ¶ms[i].timing->dsc_cfg)) {
561 params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
|
| amdgpu_dm.c | 4114 &stream->timing.dsc_cfg))
5027 bpp = stream->timing.dsc_cfg.bits_per_pixel;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_optc.c | 1532 && !timing->dsc_cfg.ycbcr422_simple);
|
